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參數(shù)資料
| 型號(hào)： | PCM1739E |
| 英文描述： | 24-Bit, 192kHz Sampling, Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣，增強(qiáng)的多級(jí)，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 140K |
| 代理商： | PCM1739E |
12
PCM1739
FIGURE 6. Output Filter Frequency Response.
1
10
100
1k
10k
100k
10M
1M
20
0
–20
–40
–60
–80
–100
L
Log Frequency (Hz)
quency response of this filter is shown in Figure 6. By itself,
this filter is not enough to attenuate the out-of-band noise to
an acceptable level for most applications. An external low-
pass filter is required to provide sufficient out-of-band noise
rejection. Further discussion of DAC post filter circuits is
provided in the Applications Information section of this data
sheet.
FIGURE 7. Biasing External Circuits Using the V
COM
L and V
COM
R Pins.
V
COM
L AND V
COM
R OUTPUTS
Two unbuffered, DC common-mode voltage output pins,
V
COM
L (pin 17) and V
COM
R (pin 12), are brought out for
decoupling purposes. These pins are normally biased to a
DC voltage level equal to V
CC
/2. These pins may be used to
bias external circuits, but they must be connected to high
impedance nodes. Figure 7 shows examples of the proper use
of the V
COM
L and V
COM
R pins for external biasing applica-
tions.
ZERO FLAG OUTPUTS
The PCM1739 includes circuitry for detecting an all zero
data condition for the data input pin, DATA. Zero detection
for each output channel is independent from the other. If the
data for a given channel remains at a ‘0’ level for 1024
sample periods (or LRCK clock periods), a Zero Detect
condition exists for the that channel. Given that a Zero
Detect condition exists, the Zero Flag pin(s) for the corre-
sponding channel(s) will be set to a logic ‘1’ state. The zero
flag outputs include ZEROL (pin 23) and ZEROR (pin 24).
These pins can be used to operate external mute circuits, or
used as status indicators for audio signal processor,
microcontroller, or other digitally-controlled functions.
1/2
OPA2353
OPA337
C
1
V
CC
R
3
C
2
R
1
R
2
+
10
μ
F
10
μ
F
V
OUT
x
V
COM
x
PCM1739
+
Filtered
Output
x = L or R
V
CC
PCM1739
V
COM
x
+
10
μ
F
x = L or R
Buffered
V
COM
(b) Using a Voltage Follower to Buffer V
COM
when Biasing Multiple Nodes
25k
Sense
Out
25k
25k
25k
V
OUT
x
V
COM
x
V+
V–
10
μ
F
+IN
–IN
+
x = L or R
Ref
To Low-Pass
Filter Stage
PCM1739
(c) Using INA134 for DC-Coupled Output
INA134
(a) Using V
COM
To Bias A Single-Supply Filter Stage
V
CC
49.9k
1%
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