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參數(shù)資料
| 型號(hào)： | PCM1739 |
| 英文描述： | 24-Bit, 192kHz Sampling, Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣，增強(qiáng)的多級(jí)，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | PCM1739 |
8
PCM1739
FIGURE 1. System Clock Input Timing.
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1739 requires a system clock for operating the
digital interpolation filters and multi-level delta-sigma modu-
lators. The system clock is applied at the SCLK input (pin
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1739 system clock.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the CLKO output (pin 4). CLKO operates at the same
frequency as the system clock, SCLK.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1739 includes a power-on reset function. Figure 2
shows the operation of this function. The system clock input
at SCLK should be active for at least one clock period prior
to V
DD
= 2.0V. With the system clock active and V
DD
>
2.0V, the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time V
DD
> 2.0V. The PCM1739 also includes an external
reset capability using the RSTB input (pin 22). This allows
an external controller or master reset circuit to force the
PCM1739 to initialize to its reset default state. For normal
operation, RSTB should be set to a logic ‘1’.
Figure 3 shows the external reset operation and timing. The
RSTB pin is set to logic ‘0’ for a minimum of 20ns. The
RSTB pin is then set to a logic ‘1’ state, which starts the
initialization sequence, which lasts for 1024 system clock
periods.
The external reset is especially useful in applications where
there is a delay between PCM1739 power up and system
clock activation. In this case, the RSTB pin should be held
at a logic ‘0’ level until the system clock has been activated.
SYSTEM CLOCK FREQUENCY, f
SCLK,
(MHZ)
SAMPLING
FREQUENCY (f
S
)
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192kHz
128f
S
—
—
—
—
—
12.2880
24.5792
24.5760
192f
S
—
—
—
—
—
18.4320
33.8688
36.8640
256f
S
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
See Note 2
See Note 2
384f
S
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note 2
See Note 2
512f
S
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note 2
See Note 2
768f
S
12.2880
24.5760
33.8688
36.8640
See Note 1
See Note 1
See Note 2
See Note 2
NOTES: (1) The 768f
S
system clock rate is not supported for f
S
> 64kHz. (2) This system clock rate is not supported for the given sampling frequencies.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
t
SCLK
t
SCLK
f
SCLK
System Clock Pulse Width High t
SCLKH
System Clock Pulse Width Low t
SCLKL
: 7ns min
: 7ns min
2.0V
0.8V
“H”
“L”
SCLK
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