參數(shù)資料
型號(hào): PCM1738E
英文描述: 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,高級(jí)分段,音頻立體聲數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 12/33頁(yè)
文件大?。?/td> 2274K
代理商: PCM1738E
PCM1738
SBAS174B
12
FIGURE 2. Power-On Reset Timing.
FIGURE 3. Audio Data Input Formats.
AUDIO DATA INTERFACE
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1738 is comprised of
a 3-wire synchronous serial port. It includes LRCK (pin 4),
BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit
clock, used to clock the serial data present on DATA into the
audio interface’s serial shift register. Serial data is clocked
into the PCM1738 on the rising edge of BCK. LRCK is the
serial audio left/right word clock, used to latch serial data
into the serial audio interface’s internal registers.
LRCK should be synchronous to the system clock. In the
event these clocks are not synchronized, the PCM1738 can
compensate for the phase difference internally. If the phase
difference between LRCK and SCKI is greater than six bit
clocks (BCK), the synchronization is performed internally.
While the synchronization is processing, the analog output is
forced to the bipolar zero level. The synchronization typi-
cally occurs in less than one cycle of LRCK.
Ideally, it is recommended that LRCK and BCK be derived
from the system clock input or output, SCKI or SCKO. The
left/right clock (LRCK) is operated at the sampling fre-
quency, f
S
.
AUDIO DATA FORMATS AND TIMING
The PCM1738 supports industry-standard audio data formats,
including Standard Right-Justified, I
2
S, and Left-Justified. The
data formats are shown in Figure 4. Data formats are selected
using the format bits, FMT [2:0], in Control Register 18. The
default data format is 16-bit Standard. All formats require
Binary Two’s Complement, MSB-first audio data. Figure 5
shows a detailed timing diagram for the serial audio interface.
1024 System Clock Periods
Reset
Reset Removal
2.4V/max
2.0V/typ
1.6V/min
V
DD
Internal Reset
System Clock
1024 System Clocks
t
RST
Reset
Reset Removal
System Clock
Internal Reset
RST (pin 1)
50% of V
DD
Reset Pulse Width LOW
t
RST
20ns (min)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PCM1738E2K 制造商:BB 制造商全稱:BB 功能描述:24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
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