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參數(shù)資料
| 型號： | PCM1728 |
| 英文描述： | 24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位，96kHz采樣的CMOSΔ-Σ立體聲音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | PCM1728 |
9
PCM1728
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 64f
S
for
all system clock ratios (256/384/512/768f
S
).
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 8. This
enhanced multi-level delta-sigma architecture also has ad-
vantages for input clock jitter sensitivity due to the multi-
level quantizer, simulated jitter sensitivity is shown in
Figure 9.
+
Z
–1
8-Level Quantizer
+
Z
–1
+
Z
–1
–
+
Z
–1
+
+
FIGURE 7. 8-Level Delta-Sigma Modulator.
0
1
2
3
4
5
6
7
8
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
Frequency (f
S
)
FIGURE 8. Quantization Noise Spectrum.
0
100
200
300
400
500
600
125
120
115
110
105
100
95
90
85
80
D
Jitter (ps)
CLOCK JITTER
FIGURE 9. Jitter Sensitivity.
THEORY OF OPERATION
The delta-sigma section of PCM1728 is based on an 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level delta-
sigma format.
This newly developed, “Enhanced Multi-level Delta-Sigma”
architecture achieves high-grade audio dynamic performance
and sound quality.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 7. This 8-level delta-sigma modulator has
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