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參數(shù)資料
| 型號： | PCM1719 |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 立體聲音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 218K |
| 代理商： | PCM1719 |
9
PCM1719
IZD = 1
IZD = 0
RSTB = “HIGH”
RSTB = “LOW”
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Forced to BPZ
(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Normal
Zero
(2)
Normal
TABLE II. Infinite Zero Detection (IZD) Function.
OPE = 1
OPE = 0
TABLE III. Output Enable (OPE) Function.
SOFTWARE
MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ
(1)
Forced to BPZ
(1)
Enabled
Enabled
Disabled
Disabled
TABLE IV. Reset (RSTB) Function.
NOTE: (1)
∑
is disconnected from output amplifier. (2)
∑
is connected to
output amplifier.
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res
res
res
res A1
A0 res PL3 PL2 PL1 PL0 ATC
IW
LRP
IIS
ATTENUATION DATA LOAD CONTROL, LCH
Bit 8 (LDL) is used to simultaneously set analog outputs of
Lch and Rch. An output level is controlled by AL[0:7]
attenuation data when this bit is set to 1. When set to 0, an
output level is not controlled and remained at the previous
attenuation level. A LDR bit in Register 1 has an equivalent
function as the LDL. When one of LDL or LDR is set to 1,
the output level of the left and right channel is simulta-
neously controlled. The attenuation level is given by:
ATT = 20log (y/256) (dB), where y = x, when
0 ≤
x
≤
254
y = x + 1, when x = 255
X is the user-determined step number, an integer value
between 0 and 255.
Example:
let x = 255
ATT
=
20log
let x = 254
let x = 1
let x = 0
REGISTER 1
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0-7 (AR0-AR7) control the level of
attenuation.
B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
res res res res res
A1 A0
LDR
AR7 AR6AR5 AR4AR3 AR2AR1AR0
REGISTER 2
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res
res
res A1
A0 res
res
res res IZD OPE DM1 DM0 MUTE
Register 2 is used to control soft mute, digital de-emphasis,
disable, and infinite zero detect. Bit 0 is used for soft mute;
a HIGH level on bit 0 will cause the output to be muted.
Bits 1 and 2 are used to control digital de-emphasis as
shown below:
BIT 1 (DM0)
BIT 2 (DM1)
DE-EMPHASIS
0
1
0
1
0
0
1
1
De-emphasis disabled
De-emphasis enabled at 48kHz
De-emphasis enabled at 44.1kHz
De-emphasis enabled at 32kHz
Bits 3 (OPE) and 4 (IZD) are used to control the infinite zero
detection features. Tables II through IV illustrate the rela-
tionship between IZD, OPE, and RSTB (reset control):
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65,536 cycles of BCKIN,
the output will only be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
IZD controls the operation of the zero detect feature: when
IZD is “LOW”, the zero detect circuit is off. Under this
condition, no automatic muting will occur if the input is
continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65,536 cycles of BCKIN, the output will be immediately
forced to a bipolar zero state (V
CC
/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero, there
may be an audible click. PCM1719 allows the zero detect
feature to be disabled so the user can implement an external
muting circuit.
REGISTER 3
Register 3 is used to select the I/O data formats. Bit 0 (IIS)
is used to control the input data format. If the input data
source is normal (16- or 18-bit, MSB first, right-justified),
set bit 0 “LOW”. If the input format is I
2
S, set bit 0 “HIGH”.
ATT
=
20log
0
256
–
∞
ATT
=
20log
1
256
–48.16dB
ATT
=
20log
254
256
–0.068dB
255
+
1
256
0dB
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