參數(shù)資料
型號: PCM1717E
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 14/14頁
文件大?。?/td> 126K
代理商: PCM1717E
14
PCM1717
FIGURE 17. Test Block Diagram.
PGA
Digital
Lch
Rch
DEM-
PCM1717
CD
Player
DAI
11th-order
LPF
THD
Meter
0dB/60dB
30KHz LPF on
Through
For test of S/N ratio and Dynamic Range, A-filter ON.
Test Disk
Shibasoku #725
0
100
200
300
400
500
600
110
105
100
95
90
85
80
75
70
65
60
D
Clock Jitter (ps)
Multi-level
PWM
FIGURE 18. Simulation Results of Clock Jitter Sensitivity.
FIGURE 19. Simulation Method for Clock Jitter.
2
1
0
–1
2
48fs
14.4ps
TEST CONDITIONS
Figure 17 illustrates the actual test conditions applied to
PCM1717 in production. The 11th-order filter is necessary
in the production environment for the removal of noise
resulting from the relatively long physical distance between
the unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 16 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11th-
order filter is used.
EVALUATION FIXTURES
Three evaluation fixtures are available for PCM1717.
DEM-PCM1717
This evaluation fixture is primarily intended for quick evalu-
ation of the PCM1717’s performance. DEM-PCM1717 can
accept either an external clock or a user-installed crystal
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1717 does not contain a receiver chip
or an external low pass filter. DEM-PCM1717 requires a
single +5V power supply.
OUT-OF-BAND NOISE CONSIDERATIONS
Delta-sigma DACs are by nature very sensitive to jitter on
the master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons delta-
sigma DACs are prone to jitter sensitivity is the large
quantization noise when the modulator can only achieve two
discrete output levels (0 or 1). The multi-level delta-sigma
DAC has improved theoretical SNR because of multiple
output states. This reduces sensitivity to jitter. Figure 18
contrasts jitter sensitivity between a one-bit PWM type DAC
and multi-level delta-sigma DAC. The data was derived
using a simulator, where clock jitter could be completely
synthesized.
相關(guān)PDF資料
PDF描述
PCM1718 Stereo Audio DIGITAL-TO-ANALOG CONVERTER
PCM1718E Stereo Audio DIGITAL-TO-ANALOG CONVERTER
PCM1719 Stereo Audio DIGITAL-TO-ANALOG CONVERTER
PCM1719E Stereo Audio DIGITAL-TO-ANALOG CONVERTER
PCM1720 Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE
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