參數(shù)資料
型號: PCM1717
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 10/14頁
文件大?。?/td> 126K
代理商: PCM1717
10
PCM1717
DIN (pin 5)
DIN (pin 5)
Audio Data Word = 16-Bit
LRCIN (pin 4)
BCKIN (pin 6)
16
14
MSB
1
LSB
MSB
1
LSB
16
Left-channel Data
Right-channel Data
1 f/s
15
16
2
3
14
15
2
3
14
15
Audio Data Word = 18-Bit
18
16
MSB
1
LSB
MSB
1
LSB
18
17
18
2
3
16
17
2
3
16
17
FIGURE 5. “Normal” Data Input Timing.
FIGURE 6. “I
2
S” Data Input Timing.
DIN (pin 5)
DIN (pin 5)
Audio Data Word = 16-Bit
LRCIN (pin 4)
BCKIN (pin 6)
16
14
MSB
1
LSB
MSB
1
LSB
16
Left-channel Data
Right-channel Data
1 f/s
15
2
3
14
15
2
3
Audio Data Word = 18-Bit
18
16
MSB
1
LSB
MSB
1
LSB
18
17
2
3
16
17
2
3
1
2
1
2
t
BCH
t
BCL
t
LB
t
BCY
t
BL
t
DH
t
DS
50% of V
DD
50% of V
DD
50% of V
DD
LRCIN
BCKIN
DIN
BCKIN Pulsewidth (High Level)
BCKIN Pulsewidth (Low Level)
BCKIN Pulse Cycle Time
BCKIN Rising Edge
¨
LRCIN Edge
LRCIN Edge
¨
BCKIN Rising Edge
DIN Setup Time
DIN Hold Time
t
BCH
t
BCL
t
BCY
t
BL
t
LB
t
DS
t
DH
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
FIGURE 7. Data Input Timing.
Bit 1 is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is LOW, a HIGH state on LRCIN is used
for the left channel, and a LOW state on LRCIN is used for
the right channel. When bit 1 is HIGH the polarity of LRCIN
is reversed.
Bit 2 is used to select the input word length. When bit 2 is
LOW, the input word length is set for 16 bits; when bit 2 is
HIGH, the input word length is set for 18 bits.
Bit 3 is used as an attenuation control. When bit 3 is set
HIGH, the attenuation data on Register 0 is used for both
channels, and the data in Register 1 is ignored. When bit 3
is LOW, each channel has separate attenuation data.
Bits 4 through 7 are used to determine the output format, as
shown in Table V:
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
TABLE V. PCM1717 Output Mode Control.
REGISTER RESET STATES
After reset, each register is set to a predetermined state:
Register 0
Register 1
Register 2
Register 3
0000 0000 1111 1111
0000 0010 1111 1111
0000 0100 0000 0000
0000 0110 1001 0000
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