參數(shù)資料
型號: PCM1715U
英文描述: Dual Voltage Output CMOS Delta-Sigma DIGITAL-TO-ANALOG CONVERTER With On-Chip Digital Filter
中文描述: 雙電壓輸出的CMOSΔ-Σ數(shù)字至模擬轉(zhuǎn)換器,帶有片上數(shù)字濾波器
文件頁數(shù): 7/9頁
文件大?。?/td> 77K
代理商: PCM1715U
7
PCM1715U
At ATT DATA: 0XFF, output is 0dB. At ATT DATA
0X00, output is –
.
When “Muting” is chosen by output mode control, out-
put goes to –
from the present ATT level.
Moving speed from 0dB to –
is 1024/f.
Initialized (RESET) ATT level is 0dB.
(2) Versatile Output Mode [PL0 ~ PL3]
By using PL0 ~ PL3 data, up to 16 different output
modes (Lch/Rch/L+R/MUTE) can be selected to the
output of Lch and Rch, as shown in Table I.
Initialized mode is STEREO mode.
(3) De-emphasis Control (DEM)
De-emphasis function is controlled by DEM flag (H:
ON, L: OFF)
De-emphasis is enabled only at 44.1kHzfs. At other fs
frequencies, de-emphasis error is not guaranteed. Initial-
ized mode is De-emphasis OFF.
(4) Attenuator Control (ATC)
If common attenuator control of Lch and Rch is needed,
use the ATC flag (ATC = “H”). Common attenuation can
be controlled by Lch (AL0 ~ AL7) data. Initialized mode
is individual.
(5) Infinity-Zero Detection
The PCM1715 has an infinity-zero detect function which
monitors the input data and bit clock. When the input
Lch
Rch
PL0
PL1
PL2
PL3
OUTPUT
OUTPUT
NOTE
0
0
0
0
MUTE
MUTE
MUTE
0
0
0
1
MUTE
R
0
0
1
0
MUTE
L
0
0
1
1
MUTE
(L + R)/2
0
1
0
0
R
MUTE
0
1
0
1
R
R
0
1
1
0
R
L
REVERSE
0
1
1
1
R
(L + R)/2
1
0
0
0
L
MUTE
1
0
0
1
L
R
STEREO
1
0
1
0
L
L
1
0
1
1
L
(L + R)/2
1
1
0
0
(L + R)/2
MUTE
1
1
0
1
(L + R)/2
R
1
1
1
0
(L + R)/2
L
1
1
1
1
(L + R)/2
(L + R)/2
MONO
data is continuously “zero” for 8192 cycles of the bit
clock, the infinity zero detect occurs and the DAC
outputs are set to bipolar zero (1/2V
CC
).
(6) Reset
Normally, internal initialize (reset) is done automatically
at power on (V
DD
> 3.5V). The RSTB-pin (Pin 25)
accepts external forced reset by RSTB=L. During
RSTB=L, the output of the DAC is invalid, set to 1/2V
CC
after internal initialize (1024XTI clock count after
RSTB=H).
MODE CONTROL FORMAT
MC
AR3 AR4 AR5
MD
ML
AL0
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AL1 AL2
AL4 AL5 AL6 AL7 AL0
AR2
AR1
AR6 AR7 PL0 PL1 PL2 PL3 DEM ATC
MSB
AL3
MSB
LSB
TABLE I. PCM1715 Output Mode Control.
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參數(shù)描述
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