參數(shù)資料
型號: PCM1712
英文描述: DIGITAL-TO-ANALOG CONVERTER
中文描述: 數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 13/16頁
文件大?。?/td> 101K
代理商: PCM1712
13
PCM1712
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 16 for optimal values of bypass
capacitors. For applications which require very high perfor-
mance at low levels (such as keyboards, synthesizers, etc.),
it may be beneficial to provide additional bypassing on
pin 15 (V
CC1
) with a low ESR 100
μ
F capacitor. This will
eliminate stray tones which may be above the noise floor.
THEORY OF OPERATION
The delta-sigma section of PCM1712 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled 16-bit input data to 5-level
delta-sigma format.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 10. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
FIGURE 10. 5 Level
Σ
Modulator Block Diagram.
Out
48fs
In
8fs
16 Bit
+
+
+
4
3
2
1
0
5-level Quantizer
+
+
Z
–1
+
+
Z
–1
+
+
Z
–1
DGND
AGND
V
DD
V
CC
Digital
Power Supply
Analog
Power Supply
FIGURE 9. Latch-up Prevention Circuit.
POWER SUPPLY
CONNECTIONS
PCM1712 has two power supply connections: digital (V
DD
)
and analog (V
CC
). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condi-
tion, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
An application circuit to avoid a latch-up condition is shown
in Figure 9.
FIGURE 8. Latch-up Prevention Circuit.
NOTE: (1) XTO must be open.
Internal System Clock
XTI
XTO
(1)
CLKO (XTI)
External System Clock Input
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