參數(shù)資料
型號: PCM1702U
英文描述: BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
中文描述: BiCMOS工藝先進(jìn)注冊幅度20位數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 2/8頁
文件大?。?/td> 129K
代理商: PCM1702U
2
PCM1702
SPECIFICATIONS
All specifications at 25
°
C,
±
V
CC
and +V
DD
=
±
5V unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PCM1702P/U, -J, -K
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
20
Bits
DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight
110
dB
DIGITAL INPUT
Logic Family
Logic Level:
TTL/CMOS Compatible
V
IH
V
IL
I
IH
I
IL
+2.4
0
+V
DD
0.8
±
10
±
10
V
V
μ
A
μ
A
V
IH
= +V
DD
V
IL
= 0V
Data Format
Input Clock Frequency
Serial, MSB First, BTC
(1)
12.5
20.0
MHz
TOTAL HARMONIC DISTORTION + N
(2)
P/U
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
P/U, -J
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
P/U, -K
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
–92
–82
–46
–96
–83
–48
–100
–84
–50
–88
–74
–40
–92
–76
–42
–96
–80
–44
dB
dB
dB
dB
dB
dB
dB
dB
dB
ACCURACY
Level Linearity
Gain Error
Bipolar Zero Error
(5)
Gain Drift
Bipolar Zero Drift
Warm-up Time
At –90dB Signal Level
±
0.5
±
0.5
±
0.25
±
25
±
5
1
dB
%
%
±
3
0
°
C to 70
°
C
0
°
C to 70
°
C
ppm of FSR/
°
C
ppm of FSR/
°
C
minute
IDLE CHANNEL SNR
(6)
Bipolar Zero, A-weighted Filter
110
120
dB
ANALOG OUTPUT
Output Range
Output Impedance
Settling Time
Glitch Energy
±
1.2
1.0
200
mA
k
ns
(
±
0.003% of FSR, 1.2mA Step)
No Glitch Around Zero
POWER SUPPLY REQUIREMENTS
Supply Voltage Range: +V
CC
= +V
DD
+4.75
–4.75
+5.00
–5.00
+5.00
–25.00
150
+5.25
–5.25
+9.0
–41.0
250
V
V
–V
= –V
DD
Combined Supply Current: +I
CC
Combined Supply Current: –I
CC
Power Dissipation
+V
CC
= +V
DD
= +5V
–V
CC
= –V
DD
= –5V
±
V
CC
=
±
V
DD
=
±
5V
mA
mA
mW
TEMPERATURE RANGE
Operating
Storage
–25
–55
+85
+125
°
C
°
C
NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion
+ Noise
) / Signal
. (3) D/A converter sample frequency (8 x 44.1kHz; 8
x
oversampling).
(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5k
feedback and an A-weighted filter.
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