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參數(shù)資料
| 型號： | PCM1604Y |
| 英文描述： | 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣,6 -通道，增強(qiáng)的多級，Δ-Σ數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 263K |
| 代理商： | PCM1604Y |
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12
PCM1604, PCM1605
FIGURE 2. Power-On Reset Timing.
FIGURE 3. External Reset Timing.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1604 is comprised
of a 5-wire synchronous serial port. It includes LRCK (pin
41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46) and
DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2
and DATA3 into the audio interface’s serial shift registers.
Serial data is clocked into the PCM1604 on the rising edge
of BCK. LRCK is the serial audio left/right word clock. It
is used to latch serial data into the serial audio interface’s
internal registers.
Both LRCK and BCK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCK be
derived from the system clock input or output, SCKI or
SCKO. The left/right clock, LRCK, is operated at the
sampling frequency (f
S
). The bit clock, BCK, may be
operated at 48 or 64 times the sampling frequency.
AUDIO DATA FORMATS AND TIMING
The PCM1604 supports industry-standard audio data for-
mats, including Standard, I
2
S, and Left-Justified. The data
formats are shown in Figure 4. Data formats are selected
using the format bits, FMT[2:0], in Control Register 9. The
default data format is 24-bit Standard. All formats require
Binary Two’s Complement, MSB-first audio data. Figure
5 shows a detailed timing diagram for the serial audio
interface.
DATA1, DATA2 and DATA3 each carry two audio channels,
designated as the Left and Right channels. The Left channel
data always precedes the Right channel data in the serial data
stream for all data formats. Table II shows the mapping of the
digital input data to the analog output pins.
DATA INPUT
CHANNEL
ANALOG OUTPUT
DATA1
DATA1
DATA2
DATA2
DATA3
DATA3
Left
Right
Left
Right
Left
Right
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
V
OUT
5
V
OUT
6
TABLE II. Audio Input Data to Analog Output Mapping.
1024 system clocks
Reset
Reset Removal
V
CC
= V
DD
Internal Reset
2.4V
2.0V
1.6V
System Clock
(SCKI)
1024 system clocks
Reset
Reset Removal
System Clock
(SCKI)
Internal Reset
RST
t
RST(1)
NOTE: (1) t
RST
= 20ns min.
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial port
which operates asynchronously to the serial audio interface.
The serial control interface is utilized to program and read the
on-chip mode registers. The control interface includes MDO
(pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO
is the serial data output, used to read back the values of the
mode registers; MDI is the serial data input, used to program
the mode registers; MC is the serial bit clock, used to shift
data in and out of the control port and ML is the control port
latch clock.
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| PCM1604YG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1605 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SoundPlus(TM) 24-Bit. 192kHz Sampling. 6-Channel. Enhanced Multi-Level. Delta-Sigma D/A Converter |
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