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參數(shù)資料
| 型號(hào)： | PCK2510SPW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 20 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | PLASTIC, TSSOP-24 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | PCK2510SPW |
Philips Semiconductors
Product specification
PCK2510S
50–150 MHz 1:10 SDRAM clock driver
1999 Dec 13
5
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN
3
MAX
3.6
V
CC
, AV
CC
V
IH
V
IL
V
I
T
amb
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
Supply voltage
V
HIGH level input voltage
2
V
LOW level input voltage
0
0.8
V
Input voltage
0
V
CC
+70
V
°
C
Operating ambient temperature range in free air
0
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNIT
AV
CC
, V
CC
(V)
3
OTHER
MIN
MAX
V
IK
Input clamp voltage
I
I
= –18 mA
I
OH
= – 100
μ
A
I
OH
= – 12 mA
I
OH
= – 6 mA
I
OL
= 100
μ
A
I
OL
= 12 mA
I
OL
= 6 mA
V
I
= V
CC
or GND
V
= V
or GND;
I
O
= 0, outputs: LOW or HIGH
–1.2
V
MIN to MAX
V
CC
– 0.2
2.1
V
OH
HIGH level output voltage
3
V
3
2.4
MIN to MAX
–
0.2
V
OL
LOW level output voltage
3
–
0.8
V
3
–
0.55
±
5
I
I
Input current
3.6
μ
A
I
CC
Quiescent supply current
3.6
10
μ
A
I
CCA
AV
CC
power supply current
Additional supply current per
input pin
Input capacitance
AV
CC
= 3.3
30
50
μ
A
I
CC
3.3 to 3.6
One input at V
CC
– 0.6 V;
other inputs at V
CC
or GND
V
I
= V
CC
or GND
V
O
= V
CC
or GND
500
μ
A
C
I
C
O
3.3
2.8
pF
Output capacitance
3.3
5.4
pF
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
CLK
Clock frequency
50
150
MHz
Input clock duty cycle
Stabilization time
1
40
60
%
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK351 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1:10 clock distribution device with 3-State outputs |
| PCK351D | 功能描述:時(shí)鐘緩沖器 1:10 CLK DISTR DEV 3-ST OUTPUT RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK351D,112 | 功能描述:時(shí)鐘緩沖器 1:10 CLK DISTR DEV RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK351D,118 | 功能描述:時(shí)鐘緩沖器 1:10 CLK DISTR DEV RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK351DB | 功能描述:時(shí)鐘緩沖器 1:10 CLK DISTR DEV 3-ST OUTPUT RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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