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參數(shù)資料
| 型號(hào)： | PCK2509SADH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | H TYPE TAP |
| 中文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | PLASTIC, SOT-355, TSSOP-24 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 79K |
| 代理商： | PCK2509SADH |
Philips Semiconductors
Product specification
PCK2509SL
50–150 MHz 1:9 SDRAM clock driver
2000 Dec 01
6
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
CLK
Clock frequency
50
150
MHz
Input clock duty cycle
Stabilization time
1
40
60
%
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage and operating free-air temperature, C
L
= 30 pF
PARAMETER
FROM
TO
V
CC
, AV
CC
= 3.3 V
±
0.3 V
MIN
TYP
–100
UNIT
(INPUT)/CONDITION
(OUTPUT)
MAX
100
t
phase error 2
CLKIN
↑
= 100 MHz to 133 MHz
CLKIN
↑
= 66 MHz
CLKIN
↑
= 100 MHz to 133 MHz
Any Y or FBOUT
FBIN
↑
ps
–125
125
ps
t
phase error
, – jitter
1, 3
t
SK(0) 4
jitter
(peak-peak)
jitter
(cycle-cycle)1
Duty cycle reference
1
t
r1
t
f1
NOTES:
1. These parameters are not production tested.
2. This is considered as static phase offset.
3. Phase error does not include jitter. (t
phase error
= static t
phase error –
jitter
(cycle-cycle)
).
4. The t
SK(0)
specification is only valid for outputs with equal loading.
FBIN
↑
–50
50
ps
Any Y or FBOUT
200
ps
CLKIN = 66 MHz to 133 MHz
Any Y or FBOUT
–80
80
ps
|65|
F(CLKIN
>
60 MHz)
V
O
= 0.4 to 2 V
V
O
= 0.4 to 2 V
Any Y or FBOUT
47
53
%
Any Y or FBOUT
2.5
1
V/ns
Any Y or FBOUT
2.5
1
V/ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCK2509SL | H TYPE TAP |
| PCK2509S | 50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SPW | 50-150 MHz 1:9 SDRAM clock driver |
| PCK2510SLDH | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SADH | 50-150 MHz 1:10 SDRAM clock driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2509SADH,112 | 功能描述:鎖相環(huán) - PLL 50-150MHZ 1:9 SDRAM CLK DRIVER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2509SL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SLDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SPW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2510S | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:10 SDRAM clock driver |
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