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參數(shù)資料
| 型號： | PCK2509S |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-150 MHz 1:9 SDRAM clock driver |
| 中文描述： | 50-150兆赫1:9 SDRAM時鐘驅(qū)動器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 70K |
| 代理商： | PCK2509S |
Philips Semiconductors
Product specification
PCK2509S
50–150 MHz 1:9 SDRAM clock driver
2
1999 Oct 19
853–2180 22544
FEATURES
Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(t
phase
error
– jitter) at 100 to133 MHz =
±
50 ps
Jitter (peak-peak) at 100 to 133 MHz =
±
80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew
<
200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of ten outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
Inputs compatible with 2.5 V and 3.3 V ranges
DESCRIPTION
The PCK2509S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLLto precisely align,
in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2509S operates at 3.3 V V
CC
and is
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine
low-skew, low-jitter copies of CLK. Output signal duty cycles are
adjusted to 50 percent, independent of the duty cycle at CLK. Each
bank of outputs can be enabled or disabled separately via the
control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low,
the outputs are disabled to the logic–low state.
Unlike many products containing PLLs, the PCK2509S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2509S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up
and application of a fixed-frequency, fixed-phase signal at CLK, and
following any changes to the PLL reference or feedback signals. The
PLL can be bypassed for test purposes by strapping AV
CC
to ground.
The PCK2509S is characterized for operation from 0
°
C to +70
°
C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
CLK
AV
CC
V
CC
V
CC
2Y0
1Y0
2Y1
GND
1Y1
GND
2Y3
V
CC
1Y2
2Y2
GND
FBIN
GND
1Y3
1Y4
V
CC
1G
FBOUT
SW00389
2G
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic TSSOP
0
°
C to +70
°
C
PCK2509S PW
SOT355-1
相關PDF資料 |
PDF描述 |
|---|---|
| PCK2509SPW | 50-150 MHz 1:9 SDRAM clock driver |
| PCK2510SLDH | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SADH | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SL | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SA | 50-150 MHz 1:10 SDRAM clock driver |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2509SA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SADH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SADH,112 | 功能描述:鎖相環(huán) - PLL 50-150MHZ 1:9 SDRAM CLK DRIVER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2509SL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SLDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:9 SDRAM clock driver |
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