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參數(shù)資料
| 型號(hào)： | PCK2023 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | H TYPE TAP |
| 中文描述： | CK408 66/100/133/200兆赫微分系統(tǒng)的擴(kuò)頻時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 177K |
| 代理商： | PCK2023 |
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Philips Semiconductors
Product data
PCK2023
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
2001 Sep 07
21
APPLICATION NOTES
Optimum performance of the PCK2023 can only be achieved
through correct implementation in the system board. This application
note addresses many of the issues associated with integrating the
PCK2023 on a system board. Descriptions for circuit board layout
and decoupling are provided in this application note.
Circuit board layout
It is possible to generate a circuit board with the proper
characteristics using four-layer configuration. Figure 11 shows the
layer stack-up. It is critical to keep the clock signals on a plane next
to a ground plane to ensure they are ground referenced otherwise
the clock signals may experience significant distortion and added
jitter. Static signals (such as SPREAD, PWRDWN, etc.) can be
placed on a layer next to the power plane.
The components associated with the clocks should be placed on the
same layer as the PCK2023 IC. This will allow the layout to avoid
the use of vias for interconnect, thereby reducing node capacitance
and trace inductance. All components should be placed as close to
the IC as possible.
CLOCK SIGNALS
GROUND
POWER
STATIC SIGNALS
SW00857
Figure 11. Optimum board layout
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCK2057 | H TYPE TAP |
| PCK2057DGG | 70 - 190 MHz I2C differential 1:10 clock driver |
| PCK2509SLDH | 50-150 MHz 1:9 SDRAM clock driver |
| PCK2509SA | H TYPE TAP |
| PCK2509SADH | H TYPE TAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2023DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK408 66/100/133/200 MHz spread spectrum differential system clock generator |
| PCK2023DGG,512 | 制造商:NXP Semiconductors 功能描述:PLL Clock Synthesizer Dual Up to 200MHz 56-Pin TSSOP Tube Tube |
| PCK2023DL | 功能描述:鎖相環(huán) - PLL WIT -CHG 112 TO 512 PCK METHOD RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2023DL,512 | 功能描述:鎖相環(huán) - PLL WIT -CHG 112 TO 512 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2023DL,518 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 WIT -CHG 112 TO 512 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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