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參數(shù)資料
| 型號(hào)： | PCK2022RA |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CK00 (100/133 MHz) spread spectrum differential system clock generator |
| 中文描述： | CK00（100/133 MHz）的微分系統(tǒng)的擴(kuò)頻時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 100K |
| 代理商： | PCK2022RA |
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Philips Semiconductors
Product data
PCK2022RA
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2003 Jul 31
8
AC ELECTRICAL CHARACTERISTICS
V
DD3
= 3.3 V
±
5%; f
crystal
= 14.31818 MHz
Host clock outputs
T
amb
= 0 to +70
°
C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNITS
NOTES
MIN
7.5
7.35
175
175
—
45
—
MAX
7.65
N/A
700
700
150
55
150
MIN
10.0
9.85
175
175
—
45
—
MAX
10.2
N/A
700
700
150
55
150
t
PKP
HOST CLK average period
Absolute minimum host clock period
HOST CLK rise time
HOST CLK fall time
HOST_CLK cycle-to-cycle jitter
Output duty cycle
HOST CLK pin-to-pin skew
ns
ns
ns
ps
ps
%
ps
11, 14, 20
11, 14, 20
11, 15, 20
11, 15, 20
11, 12, 14, 20
11, 14, 20
11, 14, 20
Abs Min Period
t
RISE
t
FALL
t
JITTER
DUTY CYCLE
t
SKEW
Rise/Fall Match-
ing
V
crossover
REFER TO NOTES ON PAGE 9.
Rise and Fall time matching
—
20%
—
20%
11, 16, 20
40% V
OH
55% V
OH
40% V
OH
55% V
OH
V
11, 14, 20
IOCLK outputs
T
amb
= 0 to +70
°
C
LIMITS
SYMBOL
PARAMETER
33 MHz MODE
MIN
30.0
12.0
12.0
0.5
0.5
—
45
66 MHz MODE
MIN
15.0
6.0
6.0
0.5
0.5
—
45
UNITS
NOTES
MAX
N/A
N/A
N/A
2.0
2.0
200
55
MAX
N/A
N/A
N/A
2.0
2.0
200
55
t
PKP
t
PKH
t
PKL
t
RISE
t
FALL
t
JITTER
IOCLK period
IOCLK HIGH time
IOCLK LOW time
IOCLK rise time
IOCLK fall time
Cycle-to-cycle jitter
Output duty cycle
ns
ns
ns
ns
ns
ps
%
2, 3, 9, 20
5, 10, 20
6, 10, 20
8, 20
8, 20
18, 20
18, 20
DUTY CYCLE
REFER TO NOTES ON PAGE 9.
USB clock output, 48MHz
T
amb
= 0 to +70
°
C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
MIN
48.08
+167
5.05
1.0
1.0
—
45
UNITS
NOTES
MAX
f
Frequency, actual
Deviation from 48 MHz
3V48MHZCLK LOW time
3V48MHZCLK rise time
3V48MHZCLK fall time
Cycle-to-cycle jitter
Output duty cycle
MHz
ppm
ns
ns
ns
ps
%
4
4
20
8, 20
8, 20
18, 20
18, 20
f
D
t
HKL
t
RISE
t
FALL
t
JITTER
N/A
4.0
4.0
250
55
DUTY CYCLE
REFER TO NOTES ON PAGE 9.
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