參數(shù)資料
型號(hào)： PCK2020
廠商： NXP Semiconductors N.V.
英文描述： CK00 100/133MHz spread spectrum differential system clock generator
中文描述： CK00 100/133MHz微分系統(tǒng)的擴(kuò)頻時(shí)鐘發(fā)生器
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 110K
代理商： PCK2020
Philips Semiconductors
Product specification
PCK2020
CK00 (100/133MHz) spread spectrum
differential system clock generator
2000 Nov 13
11
GROUP OFFSET LIMITS
GROUP
OFFSET
MEASUREMENT LOADS (LUMPED)
MEASURE POINTS
NOTES
3V66 to PCI
1.5–3.5 ns
3V66 leads
3V66 @ 30 pf
PCI @ 30 pf
3V66 @ 1.5 V
PCI @ 1.5 V
19, 20
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V
/V
levels.
2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz.
4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host =
100 MHz.
5. T
HKH
is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7.
6. T
HKL
is measured at 0.4 V for all outputs as shown in Figure 7.
7. The time is specified from when V
DDQ
achieves its normal operating level (typical condition V
DDQ
= 3.3 V) until the frequency output is stable
and operating within specification.
8. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1 mA) JEDEC specification.
9. The average period over any 1
μ
s period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Test load is Rs = 33.2
, Rp = 49.9
.
12.Must be guaranteed in a realistic system environment.
13.Configured for V
= 0.71 V in a 50
environment.
14.Measured at crossing points.
15.Measured at 20% to 80%.
16.Determined as a fraction of 2* (Trp–Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
17.Voltage measure point (Vm = 1.25 V). V
DD
= 2.5 V.
18.Voltage measure point (Vm = 1.5 V). V
DD
= 3.3 V.
19.All offsets are to be measured at rising edges.
20.Parameters are guaranteed by design.
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PCK2021 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK00 100/133 MHz spread spectrum differential system clock generator
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