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參數(shù)資料
| 型號： | PCK2011 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Direct RAMbus Clock Generator(定向RAM總線時(shí)鐘發(fā)生器) |
| 中文描述： | 直接Rambus的時(shí)鐘發(fā)生器（定向內(nèi)存總線時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 62K |
| 代理商： | PCK2011 |
Philips Semiconductors
Preliminary specification
PCK2011
Direct Rambus
Clock Generator
1999 Jan 19
4
This configuration achieves frequency-lock between the controller
and Rambus Channel clocks (PCLK and SYNCLK). These clock
signals are matched and phase-aligned at the RMC/RAC boundary
in order to allow data transfers to occur across this boundary without
additional latency.
The main clock source drives the system clock (PCLK) to the ASIC,
and also drives the reference clock (REFCLK) to the DRCG.
REFCLK may or may not be the same frequency as PCLK. A PLL
inside the DRCG multiplies REFCLK to generate the desired
frequency for BUSCLK. BUSCLK is driven on the Rambus Channel
through a terminated transmission line. At the mid-point of the
Channel, the RAC senses BUSCLK using its own DLL for clock
alignment, followed by a fixed divide-by- 4 circuit that generates
SYNCLK.
Pclk is the clock used in the Rambus memory controller (RMC) in
the ASIC. SYNCLK is the clock used at the ASIC interface of the
RAC. The DRCG together with the Gear Ratio Logic enables the
controller to exchange data directly from the PCLK domain to the
SYNCLK domain without incurring additional latency for
synchronization. In general, PCLK and SYNCLK can run at different
frequencies, so the Gear Ratio Logic must select the appropriate M
and N dividers such that the frequencies of PCLK/M and SYNCLK/N
are equal. In one example, PCLK=133MHz and SYNCLK=100MHz,
and M=4 while N=3, giving PCLK/M = SYNCLK/N = 33MHz. Figure
4 shows an example of the clock waveforms generated with the
Gear Ratio Logic.
PCK2010
Direct Rambus
Clock Generator
(DRCG)
Gear Ratio-
Logic
/4
DLL
M
N
BUSCLK
REFCLK
RMC
PCLK
SYNCLK
RAC
RDRAMs
CONTROLLER
S
P
SW00290
Figure 1. System Clock Architecture
The ASIC drives the output clocks, Pclk and SynClk/N from the
Gear Ratio Logic to the DRCG Phase Detector inputs. The routing
of the Pclk/M and SynClk/N signal traces must be matched in
impedance and propagation delay on the ASIC as well as on the
board. These signals are not part of the Rambus Channel and their
routing must be matched by board designers.
After comparing the phases of Pclk/M and SynClk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase of
DRCG output clock, Busclk. Since the other elements in the
distributed loop have a fixed delay, adjusting Busclk adjusts the
phase of SynClk and thus the phase of SynClk/N.
In this manner, the distributed loop adjusts the phase of SynClk/N to
match that of Pclk/M, eliminating the phase error at the input of the
DRCG. When the clocks are aligned, data can be exchanged
directly from the Pclk domain to the SynClk domain.
The Gear Ratio Logic supports four clock ratios (2.0, 1.5, 1.33, and
1.0), where the ratio is defined as the ratio of Pclk/SynClk. Since
Busclk = 4*SynClk, this ratio also is equal to 4*Pclk/Busclk. Other
ratios could be used, depending on particular system
implementations.
相關(guān)PDF資料 |
PDF描述 |
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| PCK2011DL | Direct RAMbus Clock Generator |
| PCK2014A | CK98 100/133 MHz spread spectrum system clock generator |
| PCK2014ADL | CK98 100/133 MHz spread spectrum system clock generator |
| PCK2020 | CK00 100/133MHz spread spectrum differential system clock generator |
| PCK2020DL | CK00 100/133MHz spread spectrum differential system clock generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2011DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Direct RAMbus Clock Generator |
| PCK2014A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK98 100/133 MHz spread spectrum system clock generator |
| PCK2014ADL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK98 100/133 MHz spread spectrum system clock generator |
| PCK2014ADL,112 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK2014ADL,118 | 功能描述:鎖相環(huán) - PLL CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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