
Philips Semiconductors
Preliminary specification
PCK2010
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
1999 Mar 01
11
AC CHARACTERISTICS (Continued)
TEST CONDITIONS
LIMITS
SYMBOL
PARAMETER
T
amb
= 0
°
C to +70
°
C
UNIT
NOTES
Measurement loads
(lumped)
CPU@30pF,
3V66@30pF
3V66@30pF,
PCI@30pF
CPU@20pF,
IOAPIC@20pF
PCI@30pF
CPU@30pF
CPUDIV2@20pF
CPU@30pF
IOAPIC@20pF
CPU@30pF
3V66@30pF
CPU@30pF
Measure points
MIN
TYP
MAX
T
HPOFFSET
CPUCLK to 3V66 CLK, CPU
leads
3V66 CLK to PCICLK, 3V66
leads
CPUCLK to IOAPIC, CPU
leads
PCICLK to CPUCLK, CPU
leads
CPUDIV2 to CPUCLK,
CPUDIV2 leads
IOAPICCLK to CPUCLK,
IOAPIC leads
3V66 CLK to CPUCLK, 3V66
leads
CPU@1.25V,
3V66@1.5V
3V66@1.5V,
PCI@1.5V
3CPU@1.25V,
IOAPIC@1.25V
PCI@1.5V
CPU@1.25V
CPUDIV2@
CPU@1.25V
IOAPIC@20pF
CPU@1.25V
3V66@1.5V
CPU@1.25V
0.0
1.5
ns
1
T
HPOFFSET
1.5
3.5
ns
1
T
HPOFFSET
1.5
4.0
ns
1
5.8
ns
1.6
ns
3.7
ns
1.7
ns
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V
OL
/V
OH
levels.
2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133.MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK
= 100MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100MHz.
5. T
HKH
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs as shown in Figure 4.
6. T
is measured at 0.4V for all outputs as shown in Figure 4.
7. The time is specified from when V
achieves its nominal operating level (typical condition V
DDQ
= 3.3V) until the frequency output is
stable and operating within specification.
8. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4V and V
OH
= 2.4V (1mA) JEDEC specification.
9. The average period over any 1
μ
s period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 3 for measure points).
PCK2010 SPREAD SPECTRUM FUNCTION TABLE
SPREAD#
SEL133/100#
SEL1
SEL0
Intel CK133
Intel CK133
Philips PCK2010
Philips
PCK2010
48MHz PLL
pin 34
pin 28
pin 33
pin 32
Function
48MHz PLL
Function
0 (active)
0 (100MHz)
0
0
3-State to
High Impedance
Inactive
3-State to
High Impedance
100MHz, Center
Spread
±
0.5%
100MHz, Down
Spread – 0.5%
100MHz, Down
Spread – 0.5%
Test Mode
133MHz, Center
Spread
±
0.5%
133MHz, Down
Spread – 0.5%
133MHz, Down
Spread – 0.5%
3-State to
High Impedance
Inactive
0 (active)
0 (100MHz)
0
1
(Reserved)
(Reserved)
Active
0 (active)
0 (100MHz)
1
0
100MHz, Down
Spread – 0.5%
100MHz, Down
Spread – 0.5%
Test Mode
Inactive
Inactive
0 (active)
0 (100MHz)
1
1
Active
Active
0 (active)
1 (133MHz)
0
0
Active
Active
0 (active)
1 (133MHz)
0
1
(Reserved)
(Reserved)
Active
0 (active)
1 (133MHz)
1
0
133Mhz, Down
Spread – 0.5%
133Mhz, Down
Spread – 0.5%
3-State to
High Impedance
Inactive
Inactive
0 (active)
1 (133MHz)
1
1
Active
Active
1 (inactive)
0 (100MHz)
0
0
Inactive
Inactive