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參數(shù)資料
| 型號： | PCK2001M |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 14.318-150 MHz IIC 1:10 clock buffer(14.318-150 MHz IIC 1:10時(shí)鐘緩沖器) |
| 中文描述： | 14.318-150兆赫進(jìn)口證1:10時(shí)鐘緩沖器（14.318-150兆赫進(jìn)口證1:10時(shí)鐘緩沖器） |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 79K |
| 代理商： | PCK2001M |
Philips Semiconductors
Product specification
PCK2001M
14.318–150 MHz I
2
C 1:10 clock buffer
2000 May 17
7
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
TYP
9
15.2
UNIT
NOTES
1, 6
MIN
15.0
MAX
15.5
T
SDKP
T
SDKH
T
SDKL
T
SDKP
T
SDKH
T
SDKL
T
SDKP
T
SDKH
T
SDKL
T
SDRISE
T
SDFALL
T
PLH
T
PHL
T
PZL
, T
PZH
T
PLZ
, T
PHZ
DUTY CYCLE
SDRAM CLK period
SDRAM CLK HIGH time
66 MHz
2, 6, 8
5.6
7.8
8.4
ns
SDRAM CLK LOW time
3, 6, 8
5.3
7.4
8.0
SDRAM CLK period
1, 6
10.0
10.01
10.5
SDRAM CLK HIGH time
100 MHz
2, 6, 8
3.3
5.1
5.7
ns
SDRAM CLK LOW time
3, 6, 8
3.1
4.9
5.5
SDRAM CLK period
1, 6
7.4
7.5
7.7
SDRAM CLK HIGH time
133 MHz
2, 6, 8
2.6
3.2
3.8
ns
SDRAM CLK LOW time
3, 6, 8
2.1
2.8
3.5
SDRAM rise time
4, 6, 10
1.5
2.0
4.0
V/ns
SDRAM fall time
4, 6, 11
1.5
2.9
4.0
V/ns
SDRAM buffer LH propagation delay
6, 7
1.0
2.5
3.5
ns
SDRAM buffer HL propagation delay
6, 7
1.0
2.5
3.5
ns
SDRAM buffer enable time
6, 7
1.0
2.6
5.0
ns
SDRAM buffer disable time
6, 7
1.0
2.7
5.0
ns
Output Duty Cycle
Measured at 1.5 V
5, 6, 7
45
52
55
%
T
SDSKW
T
DDSKW
SDRAM Bus CLK skew
1, 6
150
250
ps
Device to device skew
250
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5 V.
2. T
SDKH
is measured at 2.4 V as shown in Figure 3.
3. T
SDKL
is measured at 0.4 V as shown in Figure 3.
4. T
SDRISE
and T
SDFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1 mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at V
CC
= 3.3 V and T
amb
= 25
°
C.
10.Typical is measured with MAX (30 pf) discrete load.
11. Typical is measured with MIN (20 pf) discrete load.
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| PCK2001MDB,112 | 功能描述:時(shí)鐘緩沖器 PII CLCK DRVR MOBILE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK2001MDB,118 | 功能描述:時(shí)鐘緩沖器 PII CLCK DRVR MOBILE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK2001MDB-T | 功能描述:時(shí)鐘緩沖器 PII CLCK DRVR MOBILE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK2001R | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14.318 . 133 MHz I2C 1:6 clock buffer |
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