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參數(shù)資料
| 型號： | PCF8820U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 67 x 101 Grey-scale/ECB colour dot matrix LCD driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC235 |
| 封裝： | BUMP, DIE-235 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 316K |
| 代理商： | PCF8820U |
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2000 Dec 07
28
Philips Semiconductors
Product specification
67
×
101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
8.1.9
D
IRECT DRIVE MODE
The voltage multiplier is in the direct drive mode
(V
LCDOUT
= V
DD2
) in the following settings (see Table 8):
If bit DM = 1 and Power-down mode (bit PD = 1)
If bit DM = 1 and display off mode (bit DOF = 1)
If bit DM = 1 and high voltage generator is disabled
(bit HVE = 0).
It is recommended to always select the direct drive mode
before switching on the voltage multiplier. This is a feature
which can be used to reduce V
LCDOUT
very quickly, or to
avoid high current when the voltage multiplier starts up.
Output V
LCDOUT
is high-impedance when bit DM = 0 and
bit PD = 1,bit DM = 0andbit DOF = 0orwhenbit DM = 0,
bit PD = 0 and bit HVE = 0.
Table 8
Output V
LCDOUT
as a function of bits DM, HVE,
PD and DOF; note 1
Note
1.
X = don’t care.
8.1.10
F
RAME FREQUENCY CALIBRATION
The PCF8820 uses on-chip software to calibrate the frame
frequency. After reset, the frame frequency calibration is
disabled (bit OC = 0). Frame frequency calibration can
only be performed if the PCF8820 is not in Power-down
mode or in the partial screen mode.
The calibration is initiated by setting bit OC = 1 and is
stopped by setting bit OC = 0. The time between
calibration start and stop must be 190
μ
s to give a frame
frequency of 77 Hz (typical value).
All other commands are allowed during a calibration.
The frame frequency calibration uses a pre-divider which
hasarangefrom1 : 1to1 : 15.Thedefaultratioafterreset
is 1 : 4. The calibration period determines the pre-divider
ratio for the oscillator frequency or external clock signal.
The resulting frame frequency is calculated by the
f
1088
equation:
where f
clk
can be either the internal oscillator clock signal
or an external clock signal source.
Figure 21 shows the resulting frame frequency at different
clock frequencies and at different pre-divider ratios, for a
calibration period of 190
μ
s.
The frame frequency calibration can also be used to set
the frame frequency to a lower than typical value with a
corresponding reduction in current consumption. The
necessary calibration period (time between calibration
start and stop) can be estimated by the equation:
190
μ
s
(
)
×
f
frame
where t
cal
is the calibration time in
μ
s and f
frame
is the
desired frame frequency in Hz.
Figure 22 shows the resulting frame frequency as a
function of the calibration period at different pre-divider
ratios at a clock frequency of 336 kHz.
8.2
Reset and initialization
After power-on the content of all internal registers
including the DDRAM are in an undefined state. A reset
pulse must be applied within a specified time to reset all
internal registers. A reset can be achieved by applying an
external reset pulse (active LOW) to pad RES. When reset
occurs within the specified time all internal registers are
reset, however the DDRAM is still undefined.
After V
DD1
has reached its minimum value, the RES input
level must be
≤
0.3V
DD1
after a maximum time t
su
(see Fig.24).
After reset the state of the PCF8820 is as follows:
Default values of bits and registers as seen in Table 3
All row and column outputs are at V
SS
(display off)
V
LCDOUT
is high-impedance
RAM data is undefined.
DM
HVE
PD
DOF
V
LCDOUT
0
0
0
1
1
1
X
X
X
0
0
X
X
1
1
X
0
0
1
X
0
X
1
0
0
X
1
0
high Z
high Z
high Z
V
DD2
V
DD2
V
DD2
internally generated V
LCD
f
frame
-------------
pre-divider ratio
×
Hz
[
]
=
t
cal
77 (Hz)
=
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