參數(shù)資料
型號(hào)： PCF88132
廠商： NXP Semiconductors N.V.
英文描述： (67 + 1) x 102 pixels matrix LCD driver
中文描述： （67 1）× 102像素矩陣LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 23/72頁(yè)
文件大小： 446K
代理商： PCF88132
2004 Mar 05
23
Philips Semiconductors
Product specification
(67 + 1)
×
102 pixels matrix LCD driver
PCF8813
10 I
2
C-BUS INTERFACE (Hs-MODE)
10.1
Characteristics of the I
2
C-bus (Hs-mode)
The I
2
C-bus Hs-mode is for bidirectional, two-line
communication between different ICs or modules with
speeds up to 3.4 MHz. The only difference between
Hs-mode slave devices and Fast-mode slave devices is
the speed at which they operate, therefore the buffers on
the SLCH and SDAH outputs
(1)
have an open-drain. This
is the same for I
2
C-bus master devices which have an
open-drain SDAH output and a combination of open-drain
pull-down and current source pull-up circuits on the SCLH
output. Only the current source of one master is enabled
at any one time, and only during Hs-mode. Both lines must
be connected to a positive supply via a pull-up resistor.
Data transfer may be initiated only when the bus is not
busy.
10.1.1
S
YSTEM CONFIGURATION
Transmitter: the device that sends the data to the bus
Receiver: the device that receives the data from the bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronisation: procedure to synchronize the clock
signals of two or more devices.
(1) In Hs-mode, SCL and SDA lines operating at the higher
frequency are referred to as SCLH and SDAH.
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.25 System configuration.
10.1.2
B
IT TRANSFER
One data bit is transferred during each clock pulse (see
Fig.26). The data on the SDAH line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as control
signals.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.26 Bit transfer.
相關(guān)PDF資料
PDF描述
PCF88132DA (67 + 1) x 102 pixels matrix LCD driver
PCF8813U (67 + 1) x 102 pixels matrix LCD driver
PCF8820 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
PCF8820U 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
PCF8831 STN RGB - 160 output row driver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF88132DA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:(67 + 1) x 102 pixels matrix LCD driver
PCF8813U 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:(67 + 1) x 102 pixels matrix LCD driver
PCF8820 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:67 x 101 Grey-scale/ECB colour dot matrix LCD driver
PCF8820U 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:67 x 101 Grey-scale/ECB colour dot matrix LCD driver
PCF8831 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 160 output row driver
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