
2000 Nov 22
15
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8812
10.3
Function set
10.3.1
PD
All LCD outputs at V
SS
(display off)
Bias generator and V
LCD
generator off; V
LCD
can be
disconnected
Oscillator off (external clock possible)
Serial bus; command; etc. function
RAM contents not cleared; RAM data can be written
V
LCD
discharged to V
SS
in Power-down mode.
10.3.2
V
When V = 0, the horizontal addressing is selected. The
data is written into the DDRAM as shown in Fig.5. When
V = 1, the vertical addressing is selected. The data is
written into the DDRAM as shown in Fig.6.
10.3.3
H
When H = 0 the commands ‘display control’, ‘set
Y address’,‘setX address’andsetthePRSbit(loworhigh
range of the high voltage generator) can be performed,
when H = 1 the others can be executed. The commands
‘write data’ and ‘function set’ can be executed in both
cases.
10.4
Display control
10.4.1
D
AND
E
The bits D and E select the display mode (see Table 2).
10.5
Set Yaddress of RAM
Y3 to Y0 defines the Y address vector address of the
display RAM (see Table 3).
Table 3
X/Yaddress range: note 1
Note
1.
In bank 8 only the LSB is accessed.
10.6
Set X address of RAM
The X address points to the columns. The range of X is 0 to 101 (65H).
10.7
Set HV-generator stages
The PCF8812 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to
2
×
V
DD2
. Other voltage multiplier factors are set via the command ‘Set HV-gen stages’ (see Tables 1 and 2).
Y
3
0
0
0
0
0
0
0
0
1
Y
2
0
0
0
0
1
1
1
1
0
Y
1
0
0
1
1
0
0
1
1
0
Y
0
0
1
0
1
0
1
0
1
0
CONTENT
ALLOWED X RANGE
bank 0 (display RAM)
bank 1 (display RAM)
bank 2 (display RAM)
bank 3 (display RAM)
bank 4 (display RAM)
bank 5 (display RAM)
bank 6 (display RAM)
bank 7 (display RAM)
bank 8 (display RAM)
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101