參數(shù)資料
型號： PCF8593
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： Low power clock/calendar(低功耗時鐘/日歷)
中文描述： REAL TIME CLOCK
文件頁數(shù)： 14/28頁
文件大小： 197K
代理商： PCF8593
1997 Mar 25
14
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
7.10
Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and V
DD
is used for tuning the oscillator (see
Chapter 14, Section 14.1). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high-impedance state. This allows the user to feed the
50 Hz reference frequency or an external high-speed
event signal into the input OSCI.
7.10.1
D
ESIGNING
When designing the printed-circuit board layout, keep the
oscillator components as close to the IC package as
possible, and keep all other signal lines as far away as
possible. In applications involving tight packing of
components, shielding of the oscillator may be necessary.
AC coupling of extraneous signals can introduce oscillator
inaccuracy.
7.11
Initialization
(see Fig.12)
Note that immediately following power-on, all internal
registers are undefined and, following a RESET pulse on
pin 3, must be defined via software. Attention should be
paid to the possibility that the device may be initially in
event-counter mode, in which event the oscillator will not
operate. Over-ride can be achieved via software.
Reset is accomplished by applying an external RESET
pulse (active LOW) at pin 3. When reset occurs only the
I
2
C-bus interface is reset. The control/status register and
all clock counters are not affected by RESET. RESET
must return HIGH during device operation.
An RC combination can also be utilized to provide a
power-on RESET signal at pin 3. In this event, the values
of the RC must fulfil the following relationship to guarantee
power-on reset (see Fig.12).
RESET input must be
≤
0.3V
DD
when V
DD
reaches V
DDmin
(or higher).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
Fig.12 RC reset.
To avoid overload of the internal diode by falling V
DD
, an external
diode should be added in parallel to R
R
if C
≥
0.2
μ
F. Note that RC
must be evaluated with the actual V
of the application, as their
value will be V
DD
rise-time dependent.
handbook, halfpage
MBD819
RESET
3
CR
RR
reset
input
VDD
8
PCF8593
VDD
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