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參數(shù)資料
| 型號： | PCF8582E-2T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PROM |
| 英文描述： | 256 x 8-bit CMOS EEPROMS with I2C-bus interface |
| 中文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, SOT-96-1, SOP-8 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 179K |
| 代理商： | PCF8582E-2T |
1997 Feb 13
12
Philips Semiconductors
Product specification
256 to 1024
×
8-bit CMOS EEPROMs with
I
2
C-bus interface
PCF85xxC-2 family
11 I
2
C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and
V
IH
with an input voltage swing from V
SS
to V
DD
; see Fig.10.
Note
1.
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
SDA input/output (pin 5)
V
IL
V
IH
V
OL
I
LO
C
I
LOW level input voltage
HIGH level input voltage
LOW level output voltage
output leakage current
input capacitance
0.8
0.7V
DD
0.3V
DD
+6.5
0.4
1
7
V
V
V
μ
A
pF
I
OL
= 3 mA; V
DD(min)
V
OH
= V
DD
V
I
= V
SS
Data retention time
t
S
data retention time
T
amb
= 55
°
C
10
years
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
f
SCL
t
BUF
clock frequency
bus free time between a STOP and START
condition
START condition hold time after which first clock
pulse is generated
LOW level clock period
HIGH level clock period
set-up time for STARt condition
data hold time
for bus compatible masters
for bus devices
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
0
4.7
100
kHz
μ
s
t
HD;STA
4.0
μ
s
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
4.7
4.0
4.7
μ
s
μ
s
μ
s
repeated start
5
0
250
4.0
1
300
μ
s
ns
ns
μ
s
ns
μ
s
note 1
t
SU;DAT
t
r
t
f
t
SU;STO
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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