參數(shù)資料
型號(hào): PCF8578U
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅(qū)動(dòng)器
英文描述: LCD row/column driver for dot matrix graphic displays
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, UUC
文件頁(yè)數(shù): 27/44頁(yè)
文件大小: 323K
代理商: PCF8578U
1998 Sep 08
27
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
12 DC CHARACTERISTICS
V
DD
= 2.5 to 6 V; V
SS
= 0 V; V
LCD
= V
DD
3.5 V to V
DD
9 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
2.
3.
4.
Outputs are open; inputs at V
DD
or V
SS
; I
2
C-bus inactive; external clock with 50% duty factor.
Resets all logic when V
DD
< V
POR
.
Periodically sampled; not 100% tested.
Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V
2
to V
5
, V
DD
and V
LCD
) when the specified current flows through one output under the following conditions
(see Table 2):
a) V
op
= V
DD
V
LCD
= 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V
2
V
LCD
6.65 V; V
5
V
LCD
2.35 V; I
LOAD
= 150
μ
A.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V
3
V
LCD
4.70 V; V
4
V
LCD
4.30 V; I
LOAD
= 100
μ
A.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
V
LCD
I
DD1
I
DD2
V
POR
supply voltage
LCD supply voltage
supply current external clock
supply current internal clock
power-on reset level
2.5
V
DD
9
0.8
6
20
1.3
6.0
V
DD
3.5 V
15
50
1.8
V
f
CLK
= 2 kHz; note 1
R
OSC
= 330 k
note 2
μ
A
μ
A
V
Logic
V
IL
V
IH
I
OL1
LOW level input voltage
HIGH level input voltage
LOW level output current at SYNC
and CLK
HIGH level output current at SYNC
and CLK
LOW level output current at SDA
leakage current at SDA, SCL, SYNC,
CLK, TEST and SA0
leakage current at OSC
input capacitance at SCL and SDA
V
SS
0.7V
DD
1
0.3V
DD
V
DD
V
V
mA
V
OL
= 1 V; V
DD
= 5 V
I
OH1
V
OH
= 4 V; V
DD
= 5 V
1
mA
I
OL2
I
L1
V
OL
= 0.4 V; V
DD
= 5 V
V
i
= V
DD
or V
SS
3
+1
mA
mA
I
L2
C
i
V
i
= V
DD
note 3
+1
5
μ
A
pF
LCD outputs
I
L3
V
DC
leakage current at V
2
to V
5
DC component of LCD drivers
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
output resistance R0 to R7 and
R8/C8 to R31/C31
output resistance R8/C8 to R31/C31
and C32 to C39
V
i
= V
DD
or V
LCD
2
±
20
+2
μ
A
mV
R
ROW
row mode; note 4
1.5
3
k
R
COL
column mode; note 4
3
6
k
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