參數(shù)資料
型號: PCF8578H
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅(qū)動器
英文描述: LCD row/column driver for dot matrix graphic displays
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 9/44頁
文件大小: 323K
代理商: PCF8578H
1998 Sep 08
9
Philips Semiconductors
Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.3
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (V
th
). V
th
is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of V
op
(V
op
= V
DD
V
LCD
), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for V
op
is obtained by equating V
off(rms)
with V
th
. Figure 4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2
Optimum LCD voltages
Table 3
Multiplex rates and resistor values for Fig.5
PARAMETER
MULTIPLEX RATE
1 : 8
1 : 16
1 : 24
1 : 32
0.739
0.800
0.830
0.850
0.522
0.600
0.661
0.700
0.478
0.400
0.339
0.300
0.261
0.200
0.170
0.150
0.297
0.245
0.214
0.193
0.430
0.316
0.263
0.230
1.447
1.291
1.230
1.196
3.370
4.080
4.680
5.190
RESISTORS
MULTIPLEX RATE (n)
n = 8
n = 16, 24, 32
R1
R2
R3
R
R
R
V
2
V
op
--------
V
3
V
op
--------
V
4
V
op
--------
V
5
V
op
--------
V
op
)
-------V
V
V
op
)
----------------------
D
V
V
off rms
)
)
-----------------------
=
V
V
th
--------
n
2
n
(
(
)
R
)
R
3
n
3
(
)
R
7.4
Power-on reset
At power-on the PCF8578 resets to a defined starting
condition as follows:
1.
Display blank
2.
1 : 32 multiplex rate, row mode
3.
Start bank, 0 selected
4.
Data pointer is set to X, Y address 0, 0
5.
Character mode
6.
Subaddress counter is set to 0
7.
I
2
C-bus interface is initialized.
Data transfers on the I
2
C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Fig.4
V
bias
/V
op
as a function of the multiplex rate.
1:8
1:16
1:32
1.0
0
0.8
MSA838
1:24
multiplex rate
0.6
0.4
0.2
Vbias
Vop
V5
V4
V3
V2
V
bias
= V
2
, V
3
, V
4
, V
5
. See Table 2.
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