參數(shù)資料
型號: PCF8573T
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Clock/calendar with Power Fail Detector
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO16
封裝: 7.50 MM, PLASTIC, MS-013, SOT-162-1, SO-16
文件頁數(shù): 7/24頁
文件大?。?/td> 198K
代理商: PCF8573T
1997 Mar 28
7
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
8
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1
Bit transfer
(see Fig.3)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals.
8.2
Start and stop conditions
(see Fig.4)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
Fig.3 Bit transfer.
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.4 Definition of start and stop conditions.
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
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