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參數(shù)資料
| 型號： | PCF8573 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Clock/calendar with Power Fail Detector |
| 中文描述： | REAL TIME CLOCK |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 198K |
| 代理商： | PCF8573 |
1997 Mar 28
8
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
8.3
System configuration
(see Fig.5)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
Fig.5 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
8.4
Acknowledge
(see Fig.6)
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by
not
generating
an acknowledge on the
last byte
that has been clocked
out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition, see Figs. 9 and 10.
Fig.6 Acknowledgment on the I
2
C-bus.
MBC602
S
START
CONDITION
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF8573P | Clock/calendar with Power Fail Detector |
| PCF8573T | Clock/calendar with Power Fail Detector |
| PCF8574 | Remote 8-bit I/O expander for I2C-bus |
| PCF8578 | LCD row/column driver for dot matrix graphic displays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8573P | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Clock/calendar with Power Fail Detector |
| PCF8573PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| PCF8573T | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:NXP Semiconductors 功能描述:Real Time Clock, 16 Pin, Plastic, SOP |
| PCF8573TD | 制造商:NXP Semiconductors 功能描述:Real Time Clock, 16 Pin, Plastic, SOP |
| PCF8573TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
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