- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367817 > PCF84C64x (NXP Semiconductors N.V.) 8-BIT SINGLE CHIP MICROCONTROLLERS PDF資料下載
參數(shù)資料
| 型號： | PCF84C64x |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 145K |
| 代理商： | PCF84C64X |
Philips Semiconductors
Application note
AN168
The I
2
C serial bus: theory and practical consideration using
Philips low-voltage PCF84Cxx and PCD33xx
μ
C families
2
1988 Dec
Rev. 1 1993 Dec
Author: Carl Fenger
INTRODUCTION
The I
2
C (Inter-IC) bus has become a popular serial bus architecture
which needs to be understood for proper implementation. On the
hardware level, I
2
C is a collection of microcomputers with integrated
I
2
C port (Philips PCD33xx, PCF84Cxxx, and many of their 80(C)51
family derivatives, plus
μ
Cs from several other manufacturers), and
a peripheral set (LCD/LED drivers, RAM, ROM, E
2
PROM,
Clock/Calendars, I/O, A/D, D/A, IR transcoders, frequency
synthesizers, audio processors, telephony ICs and various tuning
ICs for TV/radio). These devices all communicate serially over a
two-wire bus, serial data (SDA) and serial clock (SCL). The I
2
C
structure is optimized for hardwire simplicity. Parallel address and
data buses inherent in conventional systems are replaced by a
serial protocol that transmits both address and bidirectional data
over a 2-wire bus. This means that interconnecting wires are
reduced to a minimum; only V
DD
, ground, and the two-wire bus are
required to link the controller(s) with the peripherals or other
controllers. This results in reduced IC size, reduced pin count, and
simpler interconnections. An I
2
C system is therefore smaller,
simpler, and cheaper to implement than its parallel counterpart.
The data rate of the I
2
C bus (100K bits/sec, with 400K bit/sec
devices in development) makes it suited for systems that do not
require high speed. The I
2
C architecture is thus well-suited for use
in applications such as handheld products (telephone handsets,
cordless phones), television and other consumer electronics,
appliances, medical instruments, general instrumentation panels,
and any application involving human interface. Typically an I
2
C
system would be used in a control function where digitally
controllable elements are adjusted and monitored by a human user
via a central processor.
The I
2
C bus is an innovative hardware interface which provides the
software designer the flexibility to create a truly multi-master
environment. Built into the serial interface of the controllers are
status registers which monitor all possible bus conditions: bus
free/busy, bus contention, slave acknowledgement, and bus
interference. Thus an I
2
C system might include several controllers
on the same bus each with the ability to asynchronously
communicate with peripherals or each other. This provision also
provides expandability for future add-on controllers. (The I
2
C
system is also ideal for use in environments where the bus is
subject to noise. Distorted transmissions are immediately detected
by the hardware and the information presented to the software.) A
slave acknowledgement on every byte also facilitates data integrity.
An I
2
C system can be as simple or sophisticated as the operating
environment demands. Whether in a single master or multi-master
system, noisy or ‘safe’, correct system operation can be insured
under software control.
CONTROLLERS
The Philips family of I
2
C microcontrollers and microprocessors has
grown to encompass mainly devices based on the Intel 8048, 8051,
and Motorola 68000 cores. These devices have various degrees of
I
2
C port implementaion which dictates to which degree the I
2
C
protocol generation and data transmission/reception is executed in
hardware vs software. Indeed, any standard microcontroller is
capable of implementing I
2
C on a normal open-drain port, in which
case the protocol is 100% software generated (‘bit banging’). The
I
2
C port itself, even when fully hardware implemented, requires only
a handful of instructions to control and monitor the I
2
C bus. Hence,
the I
2
C port can be considered a core-independent interface.
Two families of Philips microcontrollers which include members fully
implementing the I
2
C interface on-chip are the PCF84Cxxx and
PCD33xx families of 8-bit low-voltage microcontrollers. These
micros are optimized for low-power, low-voltage (V
DD
min. = 1.8V)
and are hence ideal for battery powered, cordless products. These
families implement the 8048 instruction set, with a few instructions
deleted and replaced by I
2
C-port
Table 1.
PCF84Cxxx Family Instructions not in the
Instruction Set
Serial I/O
Register
Control
Conditional
Branch
JNTF addr
MOVA,Sn
MOV Sn,A
MOV Sn,#data
EN SI
DIS SI
DEC@Rr
DJNZ@Rr,addr
SEL MB2
SEL MB3
Table 2.PCF84Cxxx Instructions not in the 8400
Family Instruction Set
Data Moves
Flags
MOVXA,@R
CLRF0
MOVXA,@R,A
CPLF0
MOVP3A,@A
CLRF1
MOVDA,P
CPLF1
NALDP,A
ORLDP,A
*replaced by JT0, JNT0
Branch
*JNI addr
JF0 addr
JF1 addr
Control
ENTOCLK
specific instructions. The I
2
C instructions involve moving data to and
from the S0, S1, and S2 serial I/O control registers. The block
diagram of the I
2
C interface is shown in Figure 1.
SERIAL I/O INTERFACE
A block diagram of the Serial Input/Output (SIO) of the PCF84Cxxx
family is shown in Figure 1. The clock line of the serial bus (SCL)
has exclusive use of Pin 3, while the Serial Data (SDA) line shares
Pin 2 with parallel I/O signal P2.3 of port 2. Consequently, only
three I/O lines are available for port 2 when the I
2
C interface is
enabled.
Communication between the CPU and I
2
C interface takes place via
the internal bus of the microcomputer and the Serial I/O Interrupt
Request line (or via polling of status bits). Four registers are used to
store data and information controlling the operation of the interface:
data shift register S0
address register S0’
status register S1
clock control register S2
THE I
2
C BUS INTERFACE SERIAL CONTROL
REGISTERS S0, S1
All serial I
2
C transfers occur between the accumulator and register
S0. The I
2
C hardware takes care of clocking out/in the data, and
receiving/generating an acknowledge. In addition, the state of the
I
2
C bus is controlled and monitored via the bus control register S1.
A definition of the registers is as follows:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF84C122 | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| PCF84C422 | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| PCF84C81A | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| PCF84C822 | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| PCF84C846 | 8-BIT SINGLE CHIP MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF84C81 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Telecom microcontrollers |
| PCF84C81A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Telecom microcontrollers |
| PCF84C81AP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Telecom microcontroller |
| PCF84C81AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Telecom microcontroller |
| PCF84C81PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。