參數(shù)資料
型號: PCF84C41A
廠商: NXP Semiconductors N.V.
英文描述: Telecom microcontrollers
中文描述: 電信微控制器
文件頁數(shù): 11/20頁
文件大?。?/td> 161K
代理商: PCF84C41A
1996 Nov 20
11
Philips Semiconductors
Product specification
Telecom microcontrollers
PCF84C21A; PCF84C41A;
PCF84C81A
12 AC CHARACTERISTICS
V
DD
= 2.5 to 5.5 V; V
SS
= 0 V; T
amb
=
40 to +85
°
C; all voltages with respect to V
SS
; unless otherwise specified.
Table 2
I
2
C-bus timing (see Figs 15 and 16)
Notes
1.
DF stands for Division Factor: the divisor of f
xtal
(see the “PCF84CxxxA family”data sheet).
2.
Values given for ASC = 0; for ASC = 1: t
HIGH
=
; t
LOW
=
3.
4.
5.
Determined by I
2
C-bus capacitance (C
b
) and external pull-up resistor.
At maximum allowed I
2
C-bus capacitance C
b
= 400 pF.
Determined by program.
6.
If t
LOW
<
, t
SU:DAT
, independent of ASC.
SYMBOL
PARAMETER
CONDITIONS
MIN.
1
TYP.
MAX.
16
UNIT
t
r
t
f
f
xtal
rise time all outputs
fall time all outputs
clock frequency
V
DD
= 5 V; T
amb
= 25
°
C; C
L
= 50 pF
V
DD
= 5 V; T
amb
= 25
°
C; C
L
= 50 pF
see Fig.3
30
30
ns
ns
MHz
SYMBOL
PARAMETER
INPUT
(see Fig.14)
OUTPUT
(see Fig.15; note 1)
SCLK
t
HD;STA
START condition hold time
t
LOW
SCLK LOW time
; note 2
t
HIGH
SCLK HIGH time
; note 2
t
RC
t
FC
SCLK rise time
SCLK fall time
1
μ
s
0.3
μ
s
1
μ
s; note 3
0.1
μ
s; note 4
SDA
t
BUF
bus free time
4.7
μ
s; note 5
t
SU;DAT
data set-up time
250 ns
; note 6
t
HD;DAT
data hold time
0
t
RD
t
FD
t
SU;STO
SDA/P2.3 rise time
SDA/P2.3 fall time
STOP condition set-up time
1
μ
s
0.3
μ
s
1
μ
s; note 3
0.1
μ
s; note 4
f
xtal
-14
2
9
+
f
xtal
×
DF
f
xtal
-17
2
3
f
xtal
×
DF
f
xtal
-17
2
3
+
f
xtal
×
DF
xtal
f
f
xtal
-15
xtal
f
xtal
f
3
f
xtal
×
2
4
1
+
)
f
xtal
×
3 DF
4
3
f
xtal
×
DF
f
xtal
-24
t
--------------------
9
f
xtal
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