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參數(shù)資料
| 型號(hào)： | PCF84C222 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | PCF84C222 |
Philips Semiconductors
The I
2
C serial bus: theory and practical consideration using Philips
low-voltage PCF84Cxx and PCD33xx
μ
C families
Application note
AN168
1988 Dec
4
3. f
SCLK
as defined by clock control register S2 of the PCF84Cxxx
μ
C family
CC4 to CC0
Divisor of f
XTAL
(DF)
f
SCLK
(kHz) at f
XTAL
= 3.58MHz
H‘00’
forbidden
f
SCLK
(kHz) at f
XTAL
= 10MHz
—
f
SCLK
(kHz) at f
XTAL
= 16MHz
—
—
H‘01’
39
91.8
*256.4
*410.3
H‘02’
45
79.5
*222.2
*355.6
H‘03’
51
70.2
*196.1
*313.7
H‘04’
63
56.8
*158.7
*254.0
H‘05’
75
47.7
*133.3
*213.3
H‘06’
87
41.1
*114.9
*183.9
H’07’
99
36.2
*101.0
*161.6
H‘08’
123
29.1
81.3
*130.1
H‘09’
147
24.4
68.0
*108.8
H‘0A’
171
20.9
58.5
93.6
H‘0B’
195
18.4
51.3
82.1
H‘0C’
243
14.7
41.2
65.8
H‘0D’
291
12.3
34.4
55.0
H‘0E’
339
10.6
29.5
47.2
H’0F’
387
9.2
25.8
41.3
H‘10’
483
7.4
20.7
33.1
H‘11’
579
6.2
17.3
27.6
H‘12’
675
5.3
14.8
23.7
H‘13’
771
4.6
13.0
20.8
H‘14’
963
3.7
10.4
16.6
H‘15’
1155
3.1
8.7
13.9
H‘16’
1347
2.7
7.4
11.9
H‘17’
1539
2.3
6.5
10.4
H‘18’
1923
1.9
5.2
8.3
H‘19’
2307
1.6
4.3
6.9
H‘1A’
2691
1.3
3.7
5.9
H‘1B’
3075
1.2
3.3
5.2
H‘1C’
3843
0.9
2.6
4.2
H‘1D’
4611
0.8
2.2
3.5
H‘1E’
5379
0.7
1.9
3.0
H‘1F’
6147
0.6
1.6
2.6
*Not permitted in non-FAST I
2
C systems; maximum specified f
SCLK
= 100kHz.
is zero, no acknowledge is generated. This mode is temporarily
used when a master/receiver refuses the acknowledgement in order
to signal an end of transmission to the slave transmitter (see the
section on the bit counter bits BC0 to BC2 in the status register S1).
The clock control register S2 is write-only. It can be written by MOV
S2,A and MOV S2,#data.
These speeds represent the frequency of the serial clock bursts and
do not reflect the speed of the processor’s main clock (i.e., it
controls the bus speed and has no effect on the CPU’s execution
speed).
BUS ARBITRATION
Due to the wire-AND configuration of the I
2
C bus, and the
self-synchronizing clock circuitry of I
2
C masters, controllers with
varying clock speeds can access the bus without clock contention.
During arbitration, the resultant clock on the bus will have a low
period equal to the longest of the low periods; the high period will
equal the shortest of the high periods. Similarly, when two masters
attempt to drive the data line simultaneously, the data is ‘ANDed’,
the master generating a low while the other is driving a high will win
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