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    參數(shù)資料
    

    


    


    
型號：
PCF51JM64VLH

    

    
廠商：
Freescale Semiconductor

    

    
文件頁數(shù)：
9/49頁

    

    
文件大?。?/td>
0K

    

    
描述：
MCU 32BIT 64K FLASH 64-LQFP

    

    
標(biāo)準(zhǔn)包裝：
160

    

    
系列：
MCF51JM

    

    
核心處理器：
Coldfire V1
    		

    

    
芯體尺寸：
32-位
    		

    

    
速度：
50MHz
    		

    

    
連通性：
CAN，I²C，SCI，SPI，USB OTG
    		

    

    
外圍設(shè)備：
LVD，PWM，WDT
    		

    

    
輸入/輸出數(shù)：
51
    		

    

    
程序存儲(chǔ)器容量：
64KB（64K x 8）
    		

    

    
程序存儲(chǔ)器類型：
閃存
    		

    

    
RAM 容量：
16K x 8
    		

    

    
電壓 - 電源 (Vcc/Vdd)：
2.7 V ~ 5.5 V
    		

    

    
數(shù)據(jù)轉(zhuǎn)換器：
A/D 12x12b
    		

    

    
振蕩器型：
外部
    		

    

    
工作溫度：
-40°C ~ 105°C
    		

    

    
封裝/外殼：
64-LQFP
    		

    

    
包裝：
托盤
    		

    

    

    

	
    
    
    

    
    
	
    Preliminary Electrical Characteristics
    MCF51JM128 ColdFire Microcontroller, Rev. 4
    Freescale Semiconductor
    17
    The average chip-junction temperature (TJ) in C can be obtained from:
    TJ = TA + (PD  JA)
    Eqn. 1
    where:
    TA = Ambient temperature, CJA = Package thermal resistance, junction-to-ambient, C/WPD = Pint PI/OPint =
    IDD  VDD, Watts — chip internal powerPI/O = Power dissipation on input and output pins — user determined
    For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
    is:
    PD = K  (TJ + 273C)
    Eqn. 2
    Solving equations 1 and 2 for K gives:
    K = PD  (TA + 273C) + JA  (PD)
    2
    Eqn. 3
    where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
    for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
    value of TA.
    2.4
    Electrostatic Discharge (ESD) Protection Characteristics
    Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling
    precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
    can withstand exposure to reasonable levels of static without suffering any permanent damage.
    All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.
    (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
    A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification
    requirements. Complete DC parametric and functional testing is performed per the applicable device specification at room
    temperature followed by hot temperature, unless specified otherwise in the device specification.
    3 1s - Single Layer Board, one signal layer
    4 2s2p - Four Layer Board, 2 signal and 2 power layers
    Table 8. ESD and Latch-up Test Conditions
    Model
    Description
    Symbol
    Value
    Unit
    Human Body
    Series Resistance
    R1
    1500
    Storage Capacitance
    C
    100
    pF
    Number of Pulse per pin
    –
    3
    Latch-up
    Minimum input voltage limit
    –2.5
    V
    Maximum input voltage limit
    7.5
    V
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PCF51JM64VLK
 制造商:Freescale Semiconductor 功能描述:RS80L 64K FLASH 8K RAM - Trays

    

    
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PCF51JU128VHS
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