參數(shù)資料
型號： PCF51JM128VLH
廠商： Freescale Semiconductor
文件頁數(shù)： 20/49頁
文件大?。?/td> 0K
描述： MCU 32BIT 128K FLASH 64-LQFP
標準包裝： 160
系列： MCF51JM
核心處理器： Coldfire V1
芯體尺寸： 32-位
速度： 50MHz
連通性： CAN，I²C，SCI，SPI，USB OTG
外圍設備： LVD，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲器容量： 128KB（128K x 8）
程序存儲器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
Preliminary Electrical Characteristics
MCF51JM128 ColdFire Microcontroller, Rev. 4
Freescale Semiconductor
27
2.10
MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125
C Ambient)
Num C
Rating
Symbol
Min
Typical1
1 Data in Typical column was characterized at 5.0 V, 25C or is typical recommended value
Max
Unit
1P
Internal reference frequency - factory trimmed at VDD
= 5 V and temperature = 25
C
fint_ft
—
32.768
—
kHz
2
P Average internal reference frequency – untrimmed
fint_ut
31.25
—
39.0625
kHz
3
T Internal reference startup time
tirefst
—60
100
s
4
P DCO output frequency
range - untrimmed 2
Low range (DRS=00)
fdco_ut
16
—
20
MHz
P
Mid range (DRS=01)
32
—
40
P
High range (DRS=10)
48
—
60
5
P DCO output frequency2
Reference =32768Hz
and DMX32 = 1
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
Low range (DRS=00)
fdco_DMX32
—
19.92
—
MHz
P
Mid range (DRS=01)
—
39.85
—
P
High range (DRS=10)
—
59.77
—
6D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
f
dco_res_t
—
0.1
0.2
%fdco
7D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
f
dco_res_t
—
0.2
0.4
%fdco
8D
Total deviation of trimmed DCO output frequency over
voltage and temperature
f
dco_t
—
0.5
–1.0
2%f
dco
9D
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0 – 70
C
f
dco_t
—
0.5
1%f
dco
10
D FLL acquisition time 3
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.
tfll_acquire
——
1
ms
11
D PLL acquisition time 4
4 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
tpll_acquire
——
1
ms
12
D
Long term Jitter of DCO output clock (averaged over
2ms interval) 5
CJitter
—0.02
0.2
%fdco
13
D VCO operating frequency
fvco
7.0
—
55.0
MHz
14
D Jitter of PLL output clock measured over 625 ns6
fpll_jitter_625ns
—0.5665
—%fpll
15
D Lock entry frequency tolerance 7
Dlock
1.49
—
2.98
%
16
D Lock exit frequency tolerance 8
Dunl
4.47
—
5.97
%
17
D Lock time — FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t
)
s
18
D Lock time — PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_r
ef)
s
19
D
Loss of external clock minimum frequency – RANGE
= 0
floc_low
(3/5) x fint
—
kHz
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