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| 型號(hào)： | PCF51AC256BCPUE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 28/42頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU 8BIT 256K FLASH 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | MCF51AC |
| 核心處理器： | Coldfire V1 |
| 芯體尺寸： | 32-位 |
| 速度： | 50MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | LVD，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲(chǔ)器容量： | 256KB（256K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 20x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
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MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor
34
2.11.1
Control Timing
Figure 11. Reset Timing
Figure 12. IRQ/KBIPx Timing
Table 17. Control Timing
Num
C
Parameter
Symbol
Min
Typical1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 C unless otherwise stated.
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
dc
—
24
MHz
2
D
Internal low-power oscillator period
tLPO
800
—
1500
s
3D
External reset pulse width2
(tcyc = 1/fSelf_reset)
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst
100
—
ns
4
D
Reset low drive
trstdrv
66
t
cyc
——
ns
5
D
Active background debug mode latch setup time
tMSSU
500
—
ns
6
D
Active background debug mode latch hold time
tMSH
100
—
ns
7D
IRQ pulse width
Asynchronous path2
Synchronous path3
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5
t
cyc
——
ns
8D
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5
t
cyc
——
ns
9D
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 C to 105 C.
tRise, tFall
—
11
35
40
75
—ns
textrst
RESET PIN
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
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