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參數(shù)資料
| 型號： | PCF50732H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732H |
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1999 May 03
14
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
Offset compensation measurement can be done on three
channels separately: baseband receive I channel,
baseband receive Q channel and AUXADC channel. All
AUXADC channels use the same offset compensation
value. Starting an offset measurement is done by writing a
logic 1 into the offset trigger register for each channel that
needs calibration. If the value ‘7’ (decimal) is written into
the offset trigger register offsets will be measured for I, Q
and AUXADC channels.
Offsets can also be read or written directly. Each offset
measurement is implemented internally as an AUXADC
measurement and takes approximately 100
μ
s.
Offsets from
256 up to 255 can be compensated.
Table 4
Connection of BSI receive signals to the
PCF5087X
PCF50732
PCF5087X
PIN
I/O
PIN
I/O
RXON
BDIO
BOEN
BIOCLK
I
RFSIG[z]
SIOXD
SIXEN_N
SIOXCLK
O
I/O
I
I
I/O
O
O
9.3.4
B
ASEBAND
S
ERIAL
I
NTERFACE
(BSI)
TIMING CHARACTERISTICS
handbook, full pagewidth
MGR990
t39
t9
t10
d.c.
(2)
logic 1s
logic 1s
data
data
data
data
d.c.
d.c.
B(0)
B(n)
B(1)
t6
t7
t42
t44
t40
ramp-up
32 QB
intermediate ramp
32 QB
trail
2 BIOCLK
clocks
ramp-down
32 QB
t43
high-Z
high-Z
high-Z
high-Z
BIOCLK
AUXDAC3
TXI/Q
(1)
BDIO
BIEN
TXON
t5
Fig.5 Timing of the baseband serial interface transmit path; for the timing values see Table 5
(1) TXI/Q = transmit I or Q.
(2) d.c. = don’t care; will be overwritten with logic 1.
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