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參數(shù)資料
| 型號： | PCF50732 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | 用于GSM基帶和音頻接口 |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732 |
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1999 May 03
26
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
12.3.2
AUXDAC1 (AGC)
VALUE AND
AUXDAC2 (AFC)
VALUE REGISTERS
Table 14
Registers overview
X = don’t care during a read/or write access.
Table 15
AUXDAC1 (AGC) value and AUXDAC2 (AFC) value registers value description
12.3.3
B
URST CONTROL REGISTER
The Burst control register controls the timing of the transmit burst (TX-burst). The ‘lo’-registers contain the lower 8 bits,
the ‘hi’-registers the upper 4 bits of a 12-bit delay value. Therefore, each register has a programmable range
from 0 to 4095. Not all combinations of values might make sense e.g. ramp-down before ramp-up.
Table 16
Burst control register (address 001 and subaddresses)
X = don’t care during a read/or write access.
Notes
1.
2.
The programming is described in Section 9.3.2.2.
The subaddress positions bit 9 (s1) and bit 8 (s0) do not apply to the DAC3 burst RAM data register.
ADDR.
REGISTER NAME
VALUE
11
10
9
8
7
6
5
4
3
2
1
0
0001
0010
AUXDAC1 (AGC) value register
AUXDAC2 (AFC) value register
X
X
X
b9
X
b8
b7
b7
b6
b6
b5
b5
b4
b4
b3
b3
b2
b2
b1
b1
b0
b0
b11
b10
VALUE OF
SYMBOL
DESCRIPTION
AUXDAC1 (AGC) value register b7 to b0
input value to the 8-bit AUXDAC1 (fed directly into the DAC); the default
value is 85H
input value to the 8-bit AUXDAC2 (fed directly into the DAC); the default
value is 800H
AUXDAC2 (AFC) value register
b11 to b0
FUNCTION
SUBADDRESS
VALUE
11
(s3)
10
(s2)
9
(s1)
8
(s0)
7
6
5
4
3
2
1
0
RU-lo
RU-hi
RM-lo
RM-hi
RD-lo
RD-hi
BIEN0-lo
BIEN0-hi
BIEN1-lo
BIEN1-hi
Single/double burst mode
(1)
DAC3 burst RAM address
(1)
DAC3 burst RAM data
(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
b7
X
b7
X
b7
X
b7
X
b7
X
X
X
d7
b6
X
b6
X
b6
X
b6
X
b6
X
X
X
d6
b5
X
b5
X
b5
X
b5
X
b5
X
X
a5
d5
b4
X
b4
X
b4
X
b4
X
b4
X
X
a4
d4
b3
b11
b3
b11
b3
b11
b3
b11
b3
b11
X
a3
d3
b2
b10
b2
b10
b2
b10
b2
b10
b2
b10
X
a2
d2
b1
b9
b1
b9
b1
b9
b1
b9
b1
b9
X
a1
d1
b0
b8
b0
b8
b0
b8
b0
b8
b0
b8
b0
a0
d0
d9
(2)
d8
(2)
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