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參數(shù)資料
| 型號： | PCF5001T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AE, SOT-136-1, SOP-28 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 273K |
| 代理商： | PCF5001T |
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1997 Mar 04
22
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
Table 8
Numeric format to ASCII conversion
4-BIT BLOCK
CHARACTER
7-BIT BLOCK
LSB
MSB
LSB
MSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
‘0’
‘1’
‘2’
‘3’
‘4’
‘5’
‘6’
‘7’
‘8’
‘9’
‘*’
‘U’
‘ ’
‘
’
‘]’
‘[’
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
7.17
Memory Organization
The PCF5001 POCSAG decoder contains non-volatile
EEPROM memory to store four user addresses, two frame
numbers and specially programmed function bits (SPF01
to SPF32) for decoder application configuration.
The EEPROM is organized as three arrays of 38 bits each
as shown in Fig.17.
A user address (or RIC) in POCSAG code comprises of
21 bits, but the three least significant bits are coded in the
frame number and therefore not explicitly transmitted. In
the PCF5001, addresses A/B and C/D must share the
same frame number: addresses A and B reside in frame
FR1 (FR10, FR11 and FR12), addresses C and D reside
in frame FR2 (FR20, FR21 and FR22). Figure 18 shows an
example of decimal address to EEPROM content
conversion. Each address must be explicitly enabled by
resetting of the associated enable bit.
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