1997 Dec 16
31
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Notes
1.
LCD outputs are open-circuit; inputs at V
DD
or V
SS
; V
0
= V
DD
; bus inactive; internal or external clock with duty cycle
50% (I
DD1
only).
Resets all logic when V
DD
< V
POR
.
When the voltages are above or below the supply voltages V
DD
or V
SS
, an input current may flow; this current must
not exceed
±
0.5 mA.
Tested on sample basis.
Resistance of output terminals (R1 to R32 and C1 to C60) with load current I
load
= 150
μ
A; V
OP
= V
DD
V
LCD
= 9 V;
outputs measured one at a time.
LCD outputs open-circuit.
2.
3.
4.
5.
6.
Logic
V
IL1
LOW level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
HIGH level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
LOW level input voltage pin OSC
HIGH level input voltage pin OSC
pull-up current at pins DB0 to DB7,
RS and R/W
LOW level output current pins
DB0 to DB7
HIGH level output current pins
DB0 to DB7
leakage current pins OSC, E, RS,
R/W, DB0 to DB7 and SA0
V
SS
0.3V
DD
V
V
IH1
0.7V
DD
V
DD
V
V
IL(osc)
V
IH(osc)
I
pu
V
SS
V
DD
0.1
0.04
0.15
V
DD
1.5
V
DD
1.00
V
V
μ
A
V
I
= V
SS
I
OL(DB)
V
OL
= 0.4 V; V
DD
= 5 V
1.6
mA
I
OH(DB)
V
OH
= 4 V; V
DD
= 5 V
1.0
mA
I
L1
V
I
= V
DD
or V
SS
1
+1
μ
A
I
2
C-bus
SDA, SCL
V
IL2
V
IH2
I
L2
C
i
I
OL(SDA)
LOW level input voltage
HIGH level input voltage
leakage current
input capacitance
LOW level output current (SDA)
note 3
note 3
V
I
= V
DD
or V
SS
note 4
V
OL
= 0.4 V; V
DD
= 5 V
V
SS
0.7V
DD
1
3
0.3V
DD
V
DD
+1
7
V
V
μ
A
pF
mA
LCD outputs
R
ROW
row output resistance pins
R1 to R32
column output resistance pins
C1 to C60
bias voltage tolerance pins
R1 to R32 and C1 to C60
note 5
1.5
3
k
R
COL
note 5
3
6
k
V
tol1
note 6
±
20
±
130
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT