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參數(shù)資料
| 型號： | PCE84C882 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller for monitor OSD and auto-sync applications(監(jiān)視器屏幕顯示和自動同步應(yīng)用的微控制器) |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 409K |
| 代理商： | PCE84C882 |
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1996 Jan 08
9
Philips Semiconductors
Preliminary specification
Microcontroller for monitor OSD
and auto-sync applications
PCE84C882
7
ANALOG (DC) CONTROL
The PCE84C882 has eight Pulse Width Modulated (PWM)
outputs for analog control purposes e.g. brightness,
contrast, H-shift, V-shift, H-width, V-size, E-W, R (or G or
B) gain control etc. Each PWM output generates a pulse
pattern with a programmable duty cycle.
The eight PWM outputs are specified below:
3 PWM outputs with 6-bit resolution (PWM4, 6 and 7)
4 PWM outputs with 7-bit resolution (PWM0 to PWM3)
1 PWM output with 14-bit resolution (PWM8).
The 6 and 7-bit PWM outputs are described in Section 7.1;
the 14-bit PWM output is described in Section 7.2 and a
typical PWM output application is described in Section 7.3.
7.1
6 and 7-bit PWM outputs
PWM outputs PWM0 to PWM4, PWM6 and PWM7, share
the same pins as Derivative Port lines DP00 to DP04,
DP06 and DP07, respectively. Selection of the pin function
as either a PWM output or a Derivative Port line is
achieved using the appropriate PWMnE bit in Register 21
(see Table 38).
The polarity of the PWM outputs is programmable and is
selected by the P7LVL or the P6LVL bit in Register 23
(see Section 12.2). The state of the P7LVL bit determines
the polarity of the 7-bit PWMs; the state of the P6LVL bit
determines the polarity of the 6-bit PWMs.
The duty cycle of each PWM output is dependent upon the
programmable contents of its associated data latch
(Registers 10 to 17 respectively, Register 15 is not used
as there is no PWM5 output). As the clock frequency of
each PWM circuit is
1
3
×
f
xtal
, the pulse width of the pulse
generated can be calculated as shown below.
Where (PWMn) is the decimal value held in the data latch.
The maximum repetition frequency (f
PWM
) of the 6 and
7-bit PWM outputs is shown below.
For the 6-bit PWM outputs:
For the 7-bit PWM outputs:
The block diagram for the 6 and 7-bit PWM outputs is
shown in Fig.5.
Pulse width
3
PWMn
f
xtal
(
)
×
=
f
PWM
f
192
=
f
PWM
f
384
---------
=
Fig.5 Block diagram for 6 and 7-bit PWMs.
handbook, full pagewidth
MLC069
DP0x data
I/O
DP0x/PWMx
6 or 7-BIT PWM DATA LATCH
P6LVL/P7LVL
internal data bus
PWMnE
6 or 7-BIT DAC PWM
CONTROLLER
Q
Q
fxtal
3
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