參數(shù)資料
型號: PCD5091H
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: DECT baseband controller
中文描述: TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100
封裝: 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-317-2, QFP-100
文件頁數(shù): 8/16頁
文件大?。?/td> 128K
代理商: PCD5091H
1997 Jul 21
8
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5091
DCK
27
25
I/O
input
ISF2DPES
ISF2UPES
ADPCM output or IOM data clock
input/output (ISF2UPES in PCD5090/xxx,
PCA5097/xxx)
ADPCM or IOM data input
8 kHz framing input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
ADPCM or IOM data output
crystal oscillator output
crystal oscillator input
analog output from D/A converter
negative supply voltage for the oscillator
positive supply voltage for the oscillator
negative input from line interface
positive input from line interface
negative supply voltage for analog circuits
negative input from microphone
positive input from microphone
positive microphone supply voltage (+2 V)
reference voltage (+2 V)
bandgap output voltage (+1.25 V)
positive supply voltage for analog circuits
negative output to earpiece
positive output to earpiece
watchdog enable input
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
general purpose 6.912 MHz output
data after clock recovery network
R_DATA comparator output
positive supply voltage 1 for the +5 V
interface
bidirectional 80C51 port pin
bidirectional 80C51 port pin
DI
FS1
28
29
26
27
I
DIPP0PES
ISF2DPES
ISF2UPES
ISI8DPES
ANAIOD1
ANAIOD1
ANAIOD1
supply
supply
ANAIOD1
ANAIOD1
supply
ANAIOR1
ANAIOR1
ANAIOD1
ANAIOD1
ANAIOR1
supply
ANAIOD1
ANAIOD1
DIUP0PES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISP2DPES
ISP2DPES
ISP2DPES
supply
I/O
input
DO
XTAL2
XTAL1
VANLO
V
SSO
V
DDO
LIFM
LIFP
V
SSA
MICM
MICP
VMIC
V
ref
VBGP
V
DDA
EARM
EARP
EN_WATCHDOG
P1.0
P1.1
P1.2
GP_CLK7
DPLL_DATA
R_SLICED
V
DD5V_1
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
O
O
I
O
I
I
I
I
O
O
O
O
O
I
I/O
I/O
I/O
O
O
O
off
running
1.0 V
0.7 V
0.7 V
0.7 V
0.7 V
off
2.0 V
1.25 V
1.4 V
1.4 V
H
H
H
L
L
L
P1.3
P1.4
55
56
53
54
I/O
I/O
H
H
ISQ2CPES
ISQ2CPES
SYMBOL
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
PIN DESCRIPTION
QFP100 LQFP100
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