參數資料
型號: PCD5002
廠商: NXP Semiconductors N.V.
英文描述: Advanced POCSAG and APOC-1 Paging Decoder
中文描述: 高級POCSAG碼和載脂蛋白C - 1尋呼解碼器
文件頁數: 23/48頁
文件大?。?/td> 203K
代理商: PCD5002
1997 Jun 24
23
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 21
Alert set-up register (04H; write)
Note
1.
Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address codeword, which designate the
POCSAG call type as shown in Table 1.
BIT (MSB D7)
VALUE
DESCRIPTION
D0
0
1
0
1
0
1
1
1
1
call alert via cadence register
POCSAG call alert (pattern selected by D7 and D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate f
AWH
, f
AWL
)
acoustic alerts enable (ATL, ATH)
vibrator alert enabled (VIB)
LED alert enabled (LED)
POCSAG alert pattern FC = 00, see Fig.9 (a)
POCSAG alert pattern FC = 01, see Fig.9 (b)
POCSAG alert pattern FC = 10, see Fig.9 (c)
POCSAG alert pattern FC = 11, see Fig.9 (d)
D1
D2
D3
D4
D5
D7 and D6
(1)
0 0
0 1
1 0
1 1
Fig.9 POCSAG alert patterns.
handbook, full pagewidth
MLC251
(a)
(b)
(c)
(d)
D7, D6
0 1
1 0
1 1
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