參數(shù)資料
型號: PCD3745A
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontroller with 4.5 kbytes OTP memory and 32 kHz real-time clock
中文描述: 8位微控制器4.5字節(jié)OTP存儲器和32kHz實時時鐘
文件頁數(shù): 15/32頁
文件大?。?/td> 156K
代理商: PCD3745A
1999 Feb 02
15
Philips Semiconductors
Product specification
8-bit microcontroller with 4.5 kbytes OTP
memory and 32 kHz real-time clock
PCD3745A
handbook, full pagewidth
8-bit internal bus
8-bit internal bus
peripheral
counter
control
register
C1:
16-BIT COUNTER
C2:
16-BIT COUNTER
EC1 EC1I
C1F
CLK1
CLK2
CE/T0
C2F
INTERRUPT
LOGIC
CPU
interrupt
RTC,timer and
external interrupts
counter
interrupts
RTC
PCD3745A
TIMER
EC2 EC2I
0
0
timer overflow
timer overflow
MSC331
Fig.5 Operation of the 16-bit counters used in metering applications.
8
THE RTC, COUNTER 1 AND COUNTER 2
INTERRUPTS
As well as the CE/T0 interrupt three additional interrupt
events are defined which have the same effect as an
external interrupt (see “PCD33xxA family data sheet”).
Real Time Clock.
This interrupt is controlled by the
Clock Interrupt Flag (CIF) and the Enable Clock
Interrupt (ECI) bit both of which reside in the Clock
Control Register (see Tables 3 and 4)
Counter 1.
This interrupt is controlled by the Counter 1
Interrupt Flag (C1F) and the Enable Counter 1 Interrupt
Flag (EC1I) both of which are located in the Peripheral
Counter Control Register (see Tables 8 and 9)
Counter 2.
This interrupt is controlled by the Counter 2
Interrupt Flag (C2F) and the Enable Counter 2 Interrupt
Flag (EC2I) both of which are located in the Peripheral
Counter Control Register (see Tables 8 and 9).
To use these interrupt sources the external interrupt must
be enabled (EN I). Interrupt servicing is exactly the same
as for an external interrupt. The interrupt routine must
include instructions that will determine the interrupt source
and remove the cause of the derivative interrupt by
explicitly clearing CIF, C1F or C2F.
By not clearing these flags the microcontroller is unable to
detect interrupts of the same type. In the interrupt routine
the CE/T0 interrupt has to be deduced from the fact that
neither CIF or C1F or C2F is set. If the specific interrupt is
not used, CIF, C1F or C2F may be directly tested by the
program. Obviously, CIF, C1F or C2F can also be asserted
under program control, e.g. to generate a software
interrupt.
Although the clock interrupt and Counter 1 and Counter 2
are part of a derivative function they are linked to the
external interrupt (see Fig.6).
A clock, Counter 1 or Counter 2 interrupt request is
serviced under the following circumstances:
No interrupt routine is being processed
No external interrupt request is pending
The enable clock interrupt and enable Counter 1 and
Counter 2 interrupt bit in the derivative Clock Control
Register and Peripheral Counter Control Register
respectively is set.
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