參數(shù)資料
型號: PCD3354A
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
中文描述: 8 -雙音多頻發(fā)電機和256字節(jié)EEPROM位微控制器
文件頁數(shù): 7/32頁
文件大?。?/td> 221K
代理商: PCD3354A
1996 Dec 18
7
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF
generator and 256 bytes EEPROM
PCA3354C; PCD3354A
6
FREQUENCY GENERATOR
A versatile frequency generator section with built-in
programmable clock divider is provided (see Fig.3).
The clock divider allows the DTMF section to run either
with the main clock frequency (f
DTMF
= f
xtal
) or with a third
of it (f
DTMF
=
1
3
×
f
xtal
) depending on the state of the divider
control bit DIV3 (see Table 5). The frequency generator
includes precision circuitry for dual tone multifrequency
(DTMF) signals, which is typically used for tone dialling
telephone sets.
The TONE output can alternatively issue twelve modem
frequencies for data rates between 300 and 1200 bits/s.
In addition to DTMF and modem frequencies, two octaves
of musical scale in steps of semitones are available. Their
frequencies are provided either in purely sinusoidal form
on the TONE output or as a square wave on the port line
P1.7/MDY. The latter is typically for ringer applications in
telephone sets. If no frequency output is selected the
TONE output is in 3-state mode.
6.1
Frequency generator derivative registers
6.1.1
H
IGH AND
L
OW
G
ROUP
F
REQUENCY
R
EGISTERS
Table 3 gives the addresses, symbols and access types of the High Group Frequency (HGF) and Low Group Frequency
(LGF) registers, used to set the frequency output.
Table 3
Hexadecimal addresses, symbols, access types and bit symbols of the frequency registers
6.1.2
C
LOCK AND
M
ELODY
C
ONTROL
R
EGISTER
(MDYCON)
Table 4
Clock and Melody Control Register, MDYCON (address 13H; access type R/W)
Table 5
Description of MDYCON bits
REGISTER
ADDRESS
REGISTER
SYMBOL
ACCESS
TYPE
BIT SYMBOLS
7
6
5
4
3
2
1
0
11H
12H
HGF
LGF
W
W
H7
L7
H6
L6
H5
L5
H4
L4
H3
L3
H2
L2
H1
L1
H0
L0
7
6
5
4
3
2
1
0
0
0
0
0
0
EDCO
DIV3
EMO
BIT
SYMBOL
EDCO
DESCRIPTION
7 to 3
2
These bits are set to a logic 0.
Enable DTMF clock output. If bit EDCO = 0, then DP1.7/DCO is a general purpose
derivative port line. If bit EDCO = 1, then DP1.7/DCO is the DTMF clock output.
EDCO = 1 does not inhibit the port instructions for DP1.7/DCO. Therefore the state of
both port line and flip-flop may be read in and the port flip-flop may be written by
derivative port instructions. However, the port flip-flop of DP1.7/DCO must remain set to
avoid conflicts between DTMF clock and port outputs.
Enable DTMF clock divider. If bit DIV3 = 0, then the DTMF clock f
DTMF
= f
xtal
.
If bit DIV3 = 1, then f
DTMF
=
1
3
×
f
xtal
.
Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line.
If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port
instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read
in and the port flip-flop may be written by port instructions. However, the port flip-flop of
P1.7/MDY must remain set to avoid conflicts between melody and port outputs.
When the HGF contents are zero while EMO = 1, P1.7/MDY is in the HIGH state.
1
DIV3
0
EMO
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