
1996 Dec 18
16
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator,
256 bytes EEPROM and real-time clock
PCD3350A
From now on, it will be assumed that AD2 to AD7 will
contain the intended EEPROM page address after page
setup.
Table 16
Page setup; preset
Table 17
Page setup; auto-incrementing
7.5.2
R
EAD BYTE
Since ADDR auto-increments after a read cycle regardless
of the page boundary, successive bytes can efficiently be
read by repeating the last instruction.
Table 18
Read byte
INSTRUCTION
RESULT
MOV A, #addr
MOV ADDR, A
MOV A, #data
address of EEPROM latch
send address to ADDR
load write, erase/write or erase
data
send data to addressed EEPROM
latch
MOV DATR, A
INSTRUCTION
RESULT
MOV A, #MC2
MOV EPCR, A
MOV A, #baddr
increment mode control word
select increment mode
EEPROM Latch 0 address
(AD0 = AD1 = 0)
send EEPROM Latch 0 address
to ADDR
load 1
st
byte from Register 0
send 1
st
byte to EEPROM Latch 0
load 2
nd
byte from Register 1
send 2
nd
byte to EEPROM
Latch 1
load 3
rd
byte from Register 2
send 3
rd
byte to EEPROM
Latch 2
load 4
th
byte from Register 3
send 4
th
byte to EEPROM Latch 3
MOV ADDR, A
MOV A, R0
MOV DATR, A
MOV A, R1
MOV DATR, A
MOV A, R2
MOV DATR, A
MOV A, R3
MOV DATR, A
INSTRUCTION
RESULT
MOV A, #RDADDR
MOV ADDR, A
MOV A, DATR
load read address
send address to ADDR
read EEPROM data
7.5.3
W
RITE PAGE
The write cycle performs a logical OR between the data in
the EEPROM latches and that in the addressed EEPROM
page. To actually copy the data from the EEPROM
latches, the corresponding bytes in the page should
previously have been erased.
The EEPROM latches are preset as described in
Section 7.5.1. The actual transfer to the EEPROM is then
performed as shown in Table 19.
The last instruction also starts Timer 2. The data in the
EEPROM latches are ORed with that in the corresponding
page bytes within 5 ms. A single-byte write is simply a
special case of ‘write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by bits AD2
to AD7) and to EEPROM Latch 0 (by bits AD0 and AD1).
This allows efficient coding of multi-page write operations.
Table 19
Write page
7.5.4
E
RASE
/
WRITE PAGE
The EEPROM latches are preset as described in
Section 7.5.1. The page bytes corresponding to the
asserted flags (among F0 to F3) are erased and re-written
with the contents of the respective EEPROM latches.
The last instruction also starts Timer 2. Erasure takes
5 ms upon which Timer Register T2 reloads for another
5 ms cycle for writing. The top cycles together take 10 ms.
A single-byte erase/write is simply a special case of
‘erase/write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by AD2 to
AD7) and to EEPROM Latch 0 (by AD0 and AD1). This
allows efficient coding of multi-page erase/write
operations.
Table 20
Erase/write page
INSTRUCTION
RESULT
MOV A, #EWP + MC2
MOV EPCR, A
‘write page’ control word
start ‘write page’ cycle
INSTRUCTION
RESULT
MOV A, #EWP + MC3
MOV EPCR, A
‘erase/write page’ control word
start ‘erase/write page’ cycle