1996 Nov 21
9
Philips Semiconductors
Product specification
Pulse and DTMF diallers with redial
PCD3310; PCD3310A
7.6
Flash duration control (FLD)
Flash (or register recall) is activated by the FL key and can
be used in DTMF and pulse dialling modes.
The FL key has the same effect as placing the telephone
‘on-hook’ for a calibrated time. Pressing the FL key will
produce a timed line-break of 100 ms (min.) at the DP/FLO
output. During the conversation mode pressing FL also
acts as a chip enable. The flash pulse duration (t
FL
) is
calibrated and can be prolonged with an external resistor
and capacitor connected to the FLD input/output (see
Fig.5). The flash pulse resets the Read Address Counter
(RAC) to the address of the first entered digit of the last
number dialled. Subsequent redial is possible (see Fig.9).
The counter of the reset delay time is held for a period of
t
FL
.
7.7
TONE output (DTMF mode)
The single and dual tones which are provided at the TONE
output are filtered by an on-chip switched capacitor filter,
followed by an on-chip active RC low-pass filter. Hence,
the total harmonic distortion of the DTMF tones meets the
CEPT recommendations. The tone output has the
following states:
tone OFF; 3-state
tone ON; the associated frequencies are superimposed
on a DC level of
1
2
V
DD
.
When the DTMF mode is selected output tones are timed
in manual dialling with a minimum duration of bursts and
pauses, and in redial with a calibrated timing. Single tones
may be generated for test purposes (CE = HIGH). Each
row and column has one corresponding frequency.
High group frequencies are generated by connecting the
column to V
SS
and LOW group frequencies are generated
by forcing the row to V
DD
. The single tone frequency will be
transmitted during activation time, but it is neither
calibrated nor stored.
An on-chip reference voltage provides output tone levels
independent of the supply voltage. Table 3 shows the
frequency tolerance of the output tones for DTMF
signalling.
Fig.5 Flash pulse duration setting.
(a) Flash duration control circuit.
(b) Flash pulse timing. t
FLRC
≈
R
×
C.
ndbook, full pagewidth
MGE492
tFL
tFLRC
(a)
(b)
R
C
FLD
60
nA
FLO