參數(shù)資料
型號： PCA9698DGG,518
廠商： NXP Semiconductors
文件頁數(shù)： 42/48頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時(shí)鐘： 1MHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935278614518
PCA9698DGG-T
PCA9698DGG-T-ND
47
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
10.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see “System and Reset Characteristics” on page 308) will generate a
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – V
RST – on its positive edge, the
delay counter starts the MCU after the Time-out period – t
TOUT – has expired. The External Reset
can be disabled by the RSTDISBL fuse, see Table 27-7 on page 289.
Figure 10-4. External Reset During Operation
10.5
Brown-out Detection
ATmega328P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
CC level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as V
BOT+ =
V
BOT + VHYST/2 and VBOT- = VBOT - VHYST/2.When the BOD is enabled, and VCC decreases to a
value below the trigger level (V
BOT- in Figure 10-5 on page 47), the Brown-out Reset is immedi-
ately activated. When V
CC increases above the trigger level (VBOT+ in Figure 10-5 on page 47),
the delay counter starts the MCU after the Time-out period t
TOUT has expired.
The BOD circuit will only detect a drop in V
CC if the voltage stays below the trigger level for lon-
ger than t
Figure 10-5. Brown-out Reset During Operation
CC
VCC
RESET
TIME-OUT
INTERNAL
RESET
VBOT-
VBOT+
tTOUT
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