參數(shù)資料
型號(hào): PCA9672PW,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 13/36頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16TSSOP
標(biāo)準(zhǔn)包裝: 2,500
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
包括: POR
其它名稱(chēng): 935282747118
PCA9672PW-T
PCA9672PW-T-ND
PCA9672
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 27 May 2013
20 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset
[1]
The power-on reset circuit resets the I2C-bus logic with VDD <VPOR and set all I/Os to logic 1 (with current source to VDD).
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
[3]
The value is not tested, but verified on sampling basis.
14. Dynamic characteristics
Inputs AD0, AD1
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-5.5
V
ILI
input leakage current
1-
+1
A
Ci
input capacitance
-
3
5
pF
Table 8.
Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 9.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Fast mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
kHz
tBUF
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time (repeated)
START condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
tVD;ACK
data valid acknowledge
time
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
300
-
50
-
50
450
ns
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-300
20 + 0.1Cb[3]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[3]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-50
-
50
-
50
ns
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