PCA9670
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NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 30 May 2013
20 of 35
NXP Semiconductors
PCA9670
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
[3]
The value is not tested, but verified on sampling basis.
14. Dynamic characteristics
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
Table 9.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Fast-mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
kHz
tBUF
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time (repeated)
START condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
tVD;ACK
data valid acknowledge
time
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
300
-
50
-
50
450
ns
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-300
20 + 0.1Cb[3]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[3]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by
the input filter
-50
-
50
-
50
ns
Port timing; CL 100 pF (see Figure 14 and Figure 13)
tv(Q)
data output valid time
-
4
-
4
-
4
s
tsu(D)
data input set-up time
0
-
0
-
0
-
s
th(D)
data input hold time
4
-
4
-
4
-
s
Reset timing (see Figure 22)
tw(rst)
reset pulse width
4
-
4
-
4
-
s
trec(rst)
reset recovery time
0
-
0
-
0
-
s
trst
reset time
100
-
100
-
100
-
s
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