參數(shù)資料
型號: PCA9559PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
中文描述: 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO20
封裝: TSSOP-20
文件頁數(shù): 2/11頁
文件大?。?/td> 83K
代理商: PCA9559PWDH
Philips Semiconductors
Product data
PCA9559
5-bit multiplexed/1-bit latched 6-bit
I
2
C EEPROM DIP switch
2
2003 Jun 27
FEATURES
5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
6-bit internal non-volatile register
Internal non-volatile register programmable and readable via
I
2
C-bus
Override input forces all outputs to logic 0
5 open drain multiplexed outputs
1 open drain non-multiplexed (latched) output
5 V and 2.5 V tolerant inputs
Useful for ‘jumperless’ configuration of PC motherboards
2 address pins, allowing up to 4 devices on the I
2
C-bus
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTION
The PCA9559 is a 20-pin CMOS device consisting of one 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 2 preset values (1 set of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance or deep
sleep modes. The PCA9559 is also useful in server and
telecom/networking applications when used to replace DIP switches
or jumpers, since the settings can be easily changed via I
2
C/SMBus
without having to power down the equipment to open the cabinet.
The non-volatile memory retains the most current setting selected
before the power is turned off.
The PCA9559 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption.
The PCA9559 has 2 address pins allowing up to 4 devices to be
placed on the same I
2
C-bus or SMBus.
PIN CONFIGURATION
I
2
C SCL
I
2
C SDA
MUX_IN B
V
CC
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
MUX_IN C
MUX_IN D
MUX_IN E
MUX_OUT B
MUX_OUT C
MUX_OUT D
MUX_OUT E
SW00216
GND
9
10
A1
A0
12
11
NON_MUXED_OUT
MUX_OUT A
MUX_IN A
WP
OVERRIDE_N
MUX_SELECT
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUM-
BER
1
2
3
4
5-9
10
SYMBOL
FUNCTION
I
2
C SCL
I
2
C SDA
A1 Address
A0 Address
MUX_IN A-E
GND
Serial I
2
C-bus clock
Serial bi-directional I
2
C-bus data
A1
A0
External inputs to multiplexer
Ground
Selects MUX_IN inputs or register
contents for MUX_OUT outputs
Open drain multiplexed outputs
Open drain outputs from
non-volatile memory
Forces all outputs to logic 0
Non-volatile register write-protect
Power supply: +3.0 to +3.6 V
11
MUX_SELECT
12-16
MUX_OUT E-A
NON_MUXED_
OUT
OVERRIDE_N
WP
V
CC
17
18
19
20
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
20-Pin Plastic TSSOP
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
0 to +70
°
C
PCA9559PW
PCA9559
SOT360-1
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